Here are my minimal notes, which are incomplete catching only the high level messages. Feel free to add and correct anything!
- SME: @banach-space: sorry, I need to rely on you for a summary
- Consistent branch: @ilinpv introduced: [RFC] Consistent branches support in LLVM. @efriedma-quic asked about higher level optimisations. I believe the idea for now was to let it be user driven.
- RegisterBank Info: @LLChris talked about hand crafted code and how writing a tablegen emitter could clean this up. Thus, a NFC AArch64 patch could replace the hand crafted code. I think this must be corresponding RFC: [RFC] TableGen support for RegisterBankInfo
- Histogram vectorisation: @graham.hunter talked about the AArch64 histcount instruction, and how to support that in the loop vectoriser. @paschalis.mpeis wrote this RFC: [RFC] Vectorization support for histogram count operations. It could trigger in SPEC, and several places in the llvm test-suite.
@graham.hunter mentioned having worked on early-exits in the LoopVectorizer in the past. - TSVC2 vectorisation outliers: @sjoerdmeijer talked about tickets raised with test cases for which we are behind gcc a lot. @kbeyls suggested reviewing the labels, @banach-space a dashboard. About loop-versioning and creating loops with unit strides, @davemgreen mentioned that loopaccessanalysis or the vectoriser might be able to do that.