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About the AArch64 category
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0
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81
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January 8, 2022
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Using MacOS calling convention to call external functions
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4
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87
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March 2, 2023
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Why do sub-byte loads on AArch64 not require masking?
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11
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180
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February 11, 2023
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What is the correct sequence of IR instructions to generate subs+sbc pair?
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2
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80
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February 2, 2023
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Inlining mathematical function
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0
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151
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January 30, 2023
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Initial patches for ARM64EC (Windows 11) now posted
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8
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857
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January 25, 2023
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Where can I find arm_neon_sve_bridge.h in GCC?
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2
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83
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November 29, 2022
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RFC: volatile/const atomics should not expand to LLSC/cmpxchg loops
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6
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367
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November 22, 2022
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Is it possible to disable a specific instruction in AArch64?
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2
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160
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October 19, 2022
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Address spaces
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2
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223
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September 12, 2022
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[ARM SVE] *_ZI instructions would not be selected in loop bodies: SVEAllActive cannot see through BB boundaries
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3
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116
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September 7, 2022
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Issues with signext i1 on aarch64
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2
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226
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August 23, 2022
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[RFC] Machine Function Splitting (MFS) on AArch64
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8
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373
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August 4, 2022
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Global ISel for DBG_VALUE
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4
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160
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July 2, 2022
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Understanding AArch64 SVE Destructive types
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0
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153
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June 19, 2022
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Illegal instruction exception (perhaps due to a heap corruption)
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13
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529
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May 10, 2022
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