Code Generation

PowerPC Discuss the PowerPC backend. Mips Ask questions about the Mips backend. Common CodeGen Infrastructure This category is for common code generation infrastructure related to all backends. ARM For questions about the Arm backend. WebAssembly For questions about the WebAssembly backend. AArch64 For questions about the AArch64 backend. X86 For questions about the X86 backend. AMDGPU This category is for discussions specific to both the development of the AMDGPU target in upstream LLVM and its use inside the LLVM project and by outside compiler frontends (e.g. LLPC, Mesa). RISCV For discussing RISCV code generation in LLVM.

Topic	Replies	Views	Activity
About the Code Generation category Code Generation	4	819	January 11, 2022
Machine Scheduler: Instruction Fusion Model Code Generation	5	83	July 26, 2025
Add a field to Coverage Mapping to track instrumentation level Code Generation llvm	8	161	July 25, 2025
TableGen custom Instruction "Operand not declared in matcher" Code Generation riscv , llvm	1	25	July 25, 2025
TableGen: Defining an instruction with a shared operand and multiple register classes Code Generation	9	79	July 24, 2025
RISC-V LLVM sync-up call July 17th 2025 RISCV	0	37	July 16, 2025
Shrink Wrap Save/Restore Points Splitting Common CodeGen Infrastructure	17	679	July 10, 2025
Should the InterleavedAccessPass participated in opt-bisect-limit Code Generation	3	43	July 9, 2025
[MachineLICM] Should we set RegLimit using RegisterClassInfo::getRegPressureSetLimit()? Common CodeGen Infrastructure	1	212	July 9, 2025
[RFC] Adding SFrame support to llvm Code Generation	3	448	July 7, 2025
Size of ISelLowering.cpp files Code Generation	10	416	July 3, 2025
RISC-V LLVM sync-up call July 3rd 2025 RISCV	0	21	July 2, 2025
Are the latencies of vextractf128 correct for Zen2/3 in MCA? X86	8	151	June 30, 2025
[RFC][tblgen] Generate linker code with TableGen Common CodeGen Infrastructure	12	444	June 30, 2025
About the semantics of `TargetFrameLowering::getOffsetOfLocalArea()` Code Generation clang , llvm	0	31	June 29, 2025
[RFC] Assembly Super Optimiser Code Generation	22	2727	June 24, 2025
X86 isel bug X86 core , x86 , clang , llvm , llvm-ir	1	130	June 20, 2025
RISC-V LLVM sync-up call June 19th 2025 RISCV	0	36	June 18, 2025
PBQP codegen acceleration? Common CodeGen Infrastructure	5	151	June 18, 2025
LOH conflicting with MachineOutliner AArch64	16	502	June 11, 2025
Linking errors when using Sleef_expfx_u10rvvm2 RISCV riscv , clang	3	53	June 9, 2025
The bug for BinaryUIOpConversion of ArithToEmitC Common CodeGen Infrastructure mlir	0	35	June 9, 2025
Best way to implement a fully custom optimization + codegen pipeline using NPM Code Generation llvm	6	138	June 5, 2025
Including location information when calling `reportFatalUsageError` Common CodeGen Infrastructure llvm	2	40	June 4, 2025
[RFC] Dynamic sizes and field offsets in DWARF Code Generation debuginfo	10	287	June 4, 2025
CANCELLED RISC-V LLVM sync-up call June 5th 2025 RISCV	0	14	June 4, 2025
[RFC] Improving MachineSink sinking into Cycles Common CodeGen Infrastructure llvm	0	119	June 3, 2025
TPDE-LLVM: 10-20x Faster LLVM -O0 Back-End Code Generation llvm	5	2232	June 3, 2025
Question on rvv builtin and policies RISCV	11	171	May 25, 2025
[RFC][DwarfDebug] Fix and improve handling imported entities, types and static local in subprogram and lexical block scopes Common CodeGen Infrastructure debuginfo	11	991	May 28, 2025