Code Generation

ARM For questions about the Arm backend. Mips Ask questions about the Mips backend. AArch64 For questions about the AArch64 backend. PowerPC Discuss the PowerPC backend. AMDGPU This category is for discussions specific to both the development of the AMDGPU target in upstream LLVM and its use inside the LLVM project and by outside compiler frontends (e.g. LLPC, Mesa). WebAssembly For questions about the WebAssembly backend. X86 For questions about the X86 backend. RISCV For discussing RISCV code generation in LLVM. Common Infrastructure This category is for common code generation infrastructure related to all backends.

Topic	Replies	Views	Activity
About the Code Generation category Code Generation	4	131	January 11, 2022
Bypassing tablegen for asm/disassm Code Generation	2	33	May 18, 2022
How to spill a register in fast RA if the spilling will create another temp register Common Infrastructure x86	3	52	May 18, 2022
Code generation change between llvm 11 and 12, amd64 Code Generation	2	86	May 18, 2022
What is '~' mean in opc for SDNode Code Generation	2	45	May 17, 2022
Arm Backend's GlobalISel Status ARM globalisel	4	137	May 17, 2022
How to implement fneg pat? Code Generation	4	66	May 16, 2022
GCC vs Clang differences in protected visibility implementation Common Infrastructure	3	131	May 13, 2022
How to ensure a value is in a specific register at call sites Code Generation	4	90	May 12, 2022
Re: riscv: llvm-compiler: calling convention violation: temporary register $t2 is used to pass the ninth function parameter RISCV	1	54	May 12, 2022
Passing Information from Caller to Callee at SelectionDAG node Code Generation	7	74	May 12, 2022
RISC-V LLVM sync-up call 12th May 2022 RISCV	0	58	May 12, 2022
Initial patches for ARM64EC (Windows 11) now posted AArch64	1	91	May 12, 2022
How to find out the instruction that is causing this error? RISCV	9	198	May 11, 2022
Illegal instruction exception (perhaps due to a heap corruption) AArch64	13	126	May 10, 2022
Can tied use operands be 'isKill'? Common Infrastructure	1	65	May 4, 2022
LLVM custom backend iplementation Common Infrastructure	6	80	May 3, 2022
How to move legacy passes to new pass manager? Code Generation	2	92	April 30, 2022
Question about WriteRes records Common Infrastructure	0	66	April 29, 2022
Inverted scheduling of grouped "store" operations? WebAssembly	4	73	April 29, 2022
Try to generate assembly code with my custom backend Code Generation	2	84	April 29, 2022
Auto-generate the memory folding tables X86	16	242	April 28, 2022
CANCELLED RISC-V LLVM sync-up call 28th April 2022 RISCV	0	48	April 27, 2022
How can I control FP_EXTEND's combine? Code Generation	2	49	April 25, 2022
Why clang's float use 8bytes, It should be 4 bytes. How can I fix it? Code Generation	2	93	April 22, 2022
Matching Against Two Patterns with the Same Operand Types Code Generation	2	63	April 22, 2022
Practical way to call delphi "register" (i386) calling convention method with llvm Code Generation	1	42	April 21, 2022
SUBREG_TO_REG pseudo instruction. Could the immediate operand be of type MO_CImmediate? Common Infrastructure	1	35	April 21, 2022
TableGen how to define 64bit immediate pat? Code Generation	2	75	April 18, 2022
How to add double to my backend Code Generation	3	76	April 14, 2022