Code Generation

PowerPC Discuss the PowerPC backend. X86 For questions about the X86 backend. ARM For questions about the Arm backend. AArch64 For questions about the AArch64 backend. Mips Ask questions about the Mips backend. WebAssembly For questions about the WebAssembly backend. RISCV For discussing RISCV code generation in LLVM. AMDGPU This category is for discussions specific to both the development of the AMDGPU target in upstream LLVM and its use inside the LLVM project and by outside compiler frontends (e.g. LLPC, Mesa). Common Infrastructure This category is for common code generation infrastructure related to all backends.

Topic	Replies	Views	Activity
About the Code Generation category Code Generation	4	493	January 11, 2022
How to test register pressure Code Generation	5	132	September 27, 2023
[RFC] report_fatal_error and the default value of GenCrashDialog Common Infrastructure	6	150	September 27, 2023
[RFC] CFIFixup handling of prologues which span more than one basic block Common Infrastructure	1	15	September 27, 2023
[RFC] Matching gcc's -mlarge-data-threshold for x86-64's medium code model X86	1	27	September 27, 2023
The question about union of rvalue Code Generation	0	25	September 25, 2023
[RFC] Design for AVX10 options support X86	0	99	September 25, 2023
Unexpected branching behaviour when creating new basic blocks RISCV	3	58	September 22, 2023
[RFC] GlobalISel support for X86 X86	9	398	September 21, 2023
How to get debug location at MCCodeEmitter when source file is a C file or bitcode file? RISCV riscv , debuginfo , llvm	0	36	September 21, 2023
[RFC] MDL: A Micro-Architecture Description Language for LLVM Common Infrastructure llvm	50	16745	September 20, 2023
[RFC] Design for AVX10 feature support X86	18	1000	September 19, 2023
Should MachineCSE honor TargetRegisterInfo::shouldCoalesce()? Code Generation	0	25	September 19, 2023
Compile 128bit custom riscv instructions RISCV riscv , llvm	4	109	September 19, 2023
[AArch64][PAuthABI] Options for command line options to use the PAuthABI and set signing schema AArch64	0	70	September 15, 2023
RISC-V LLVM sync-up call September 14th 2023 RISCV	0	48	September 13, 2023
Issue with adding 72 bit registers Common Infrastructure	13	162	September 14, 2023
RuntimeDyldChecker/jitlink-check Thumb Support ARM jit	9	172	September 13, 2023
How does OrcJIT or MCJIT implement function-level parallel compilation on a huge module? Code Generation jit	0	45	September 13, 2023
Is there a way to tell wasm-ld not to create any space for the stack (that won't be used in a browser) WebAssembly	4	80	September 9, 2023
Implementing modulo variable expansion for MachinePipeliner Common Infrastructure	7	343	September 7, 2023
Why two variants of every constructor are created by the compiler? Code Generation clang	3	114	September 6, 2023
[NVPTX] Plans to support s16x2/u16x2 instructions for sm_90 Code Generation gpu	1	63	September 6, 2023
LLVM Tablegen Error while executing Code Generation	2	52	September 4, 2023
Helper script for analyzing mir dumps Code Generation	2	99	September 1, 2023
How can I model an instruction that gets broken down into two µ-ops? Code Generation	17	386	September 1, 2023
CANCELLED RISC-V LLVM sync-up call August 31st 2023 RISCV	0	61	August 30, 2023
LTO, ThinLTO, and Split DWARF Common Infrastructure lto , thinlto , debuginfo , llvm	4	400	August 30, 2023
[RFC] Design for APX feature EGPR and NDD support X86	5	284	August 28, 2023
Conv::C and Conv::PreserveMost mix badly on Windows x64 X86 windows	0	92	August 26, 2023