About the Code Generation category
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4
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493
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January 11, 2022
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How to test register pressure
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5
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132
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September 27, 2023
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[RFC] report_fatal_error and the default value of GenCrashDialog
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6
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150
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September 27, 2023
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[RFC] CFIFixup handling of prologues which span more than one basic block
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1
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15
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September 27, 2023
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[RFC] Matching gcc's -mlarge-data-threshold for x86-64's medium code model
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1
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27
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September 27, 2023
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The question about union of rvalue
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0
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25
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September 25, 2023
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[RFC] Design for AVX10 options support
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0
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99
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September 25, 2023
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Unexpected branching behaviour when creating new basic blocks
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3
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58
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September 22, 2023
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[RFC] GlobalISel support for X86
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9
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398
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September 21, 2023
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How to get debug location at MCCodeEmitter when source file is a C file or bitcode file?
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0
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36
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September 21, 2023
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[RFC] MDL: A Micro-Architecture Description Language for LLVM
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50
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16745
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September 20, 2023
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[RFC] Design for AVX10 feature support
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18
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1000
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September 19, 2023
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Should MachineCSE honor TargetRegisterInfo::shouldCoalesce()?
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0
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25
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September 19, 2023
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Compile 128bit custom riscv instructions
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4
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109
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September 19, 2023
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[AArch64][PAuthABI] Options for command line options to use the PAuthABI and set signing schema
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0
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70
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September 15, 2023
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RISC-V LLVM sync-up call September 14th 2023
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0
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48
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September 13, 2023
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Issue with adding 72 bit registers
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13
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162
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September 14, 2023
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RuntimeDyldChecker/jitlink-check Thumb Support
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9
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172
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September 13, 2023
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How does OrcJIT or MCJIT implement function-level parallel compilation on a huge module?
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0
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45
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September 13, 2023
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Is there a way to tell wasm-ld not to create any space for the stack (that won't be used in a browser)
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4
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80
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September 9, 2023
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Implementing modulo variable expansion for MachinePipeliner
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7
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343
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September 7, 2023
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Why two variants of every constructor are created by the compiler?
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3
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114
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September 6, 2023
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[NVPTX] Plans to support s16x2/u16x2 instructions for sm_90
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1
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63
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September 6, 2023
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LLVM Tablegen Error while executing
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2
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52
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September 4, 2023
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Helper script for analyzing mir dumps
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2
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99
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September 1, 2023
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How can I model an instruction that gets broken down into two µ-ops?
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17
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386
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September 1, 2023
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CANCELLED RISC-V LLVM sync-up call August 31st 2023
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0
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61
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August 30, 2023
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LTO, ThinLTO, and Split DWARF
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4
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400
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August 30, 2023
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[RFC] Design for APX feature EGPR and NDD support
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5
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284
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August 28, 2023
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Conv::C and Conv::PreserveMost mix badly on Windows x64
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0
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92
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August 26, 2023
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