About the Code Generation category
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4
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793
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January 11, 2022
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RISC-V LLVM sync-up call January 30th 2025
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0
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3
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January 29, 2025
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Newbie how to prevent constant:i32<2> from becoming i8=constant<2>
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2
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33
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January 29, 2025
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How to get the Constant FP value from a load from a constant pool?
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2
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105
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January 29, 2025
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Help Needed: Handling Redundant Instructions in RISC-V Backend DAG->DAG Pattern Selection
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3
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31
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January 28, 2025
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Adding short backtrace debuginfo
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11
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196
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January 28, 2025
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Lowering LLVM vector types in RISC-V
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2
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36
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January 28, 2025
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Issue with Executing First MachineFunctionPass
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3
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29
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January 26, 2025
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Question about address space constant writtern into object file
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0
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19
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January 23, 2025
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AArch64, naked functions, and prologue-epilogue insertion
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1
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35
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January 22, 2025
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TLS support in GPU progamming
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7
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87
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January 22, 2025
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[GlobalISel] HwModes for pointers of different sizes
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1
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42
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January 21, 2025
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Control Flow Integrity + PC-Relative VTables
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7
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163
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January 20, 2025
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Is there any document about how to implement wasm backend in LLVM
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0
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27
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January 20, 2025
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Divergent Control Flow
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23
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475
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January 20, 2025
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Using CodeGen information to modify IR
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2
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45
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January 17, 2025
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Always fold a node: duplicate the incoming node or custom selection?
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2
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31
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January 16, 2025
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RISC-V LLVM sync-up call January 16th 2025
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0
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43
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January 15, 2025
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Is noalias propagated in MachineIR after lowering?
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2
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38
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January 15, 2025
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Can't fold LOAD into user during ISel
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16
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162
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January 10, 2025
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Does RISCV RVV has any C++ syntax to create vector
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1
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60
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January 9, 2025
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Why are the branch instructions not ```isBarrier = 1```
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2
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51
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January 8, 2025
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What dose FP in ISD::INT_TO_FP mean?
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2
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44
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January 8, 2025
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How do I get desired 'align' for byVal passes of struct vars to procedure calls in IR code? Where should I look to configure that?
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0
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19
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January 7, 2025
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Extending post-regalloc MachineLICM
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3
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133
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January 6, 2025
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Shrink Wrap Save/Restore Points Splitting
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13
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369
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January 6, 2025
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I want to default to ZEXT Loads instead of SEXT on my custom backend. Where should I look to change that?
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5
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86
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January 5, 2025
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[GlobalISel] Are register banks allowed to overlap?
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7
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96
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January 2, 2025
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Maybe we need optimize READ_REGISTER AND WRITE_REGISTER
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7
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129
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December 31, 2024
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How to manage TLS from a third-party library?
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1
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70
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December 31, 2024
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