Code Generation

RISCV For discussing RISCV code generation in LLVM. Mips Ask questions about the Mips backend. PowerPC Discuss the PowerPC backend. AMDGPU This category is for discussions specific to both the development of the AMDGPU target in upstream LLVM and its use inside the LLVM project and by outside compiler frontends (e.g. LLPC, Mesa). AArch64 For questions about the AArch64 backend. WebAssembly For questions about the WebAssembly backend. Common Infrastructure This category is for common code generation infrastructure related to all backends. ARM For questions about the Arm backend. X86 For questions about the X86 backend.

Topic	Replies	Views	Activity
About the Code Generation category Code Generation	4	247	January 11, 2022
Backend Legacy PM Usage --- Help Needed! Common Infrastructure	1	39	December 2, 2022
Global Instruction Selection BPF example Common Infrastructure	2	40	December 2, 2022
Specifying unpriviledge spec version (-misa-spec gcc flag equivalent) RISCV	0	21	December 1, 2022
How to allocate consecutive registers? (Array register files?) Code Generation	4	175	November 30, 2022
On vectorization under RISC-V and its existing interface to control scalable vectorization width - vectorize_width(VF, scalable) RISCV	2	51	November 29, 2022
Where can I find arm_neon_sve_bridge.h in GCC? AArch64	2	44	November 29, 2022
How to legalize an EVT ValueType? Code Generation	1	38	November 29, 2022
Codegen document question Common Infrastructure	2	84	November 28, 2022
How Hexagon handles OperandCycles? Code Generation hexagon	3	84	November 25, 2022
How to force compiler to save registers before using it during code gen? Code Generation clang	3	79	November 24, 2022
CANCELLED RISC-V LLVM sync-up call 24th November 2022 RISCV	0	32	November 23, 2022
Cleanly Addressing GlobalISel/DAG Pattern Matching Differences Code Generation	18	535	November 23, 2022
Error when splitting v4i16 data into four i16 using DAG.ExtractVectorElements() Common Infrastructure llvm	2	61	November 23, 2022
[RFC] MDL: A Micro-Architecture Description Language for LLVM Common Infrastructure llvm	28	13715	November 22, 2022
[RFC] Any-sized VT for TableGen Code Generation	3	144	November 22, 2022
RFC: volatile/const atomics should not expand to LLSC/cmpxchg loops AArch64	6	301	November 22, 2022
Cannot auto vectorization for the half float point in RISCV RISCV riscv	3	68	November 21, 2022
Windows clang assembler and sysv_abi X86	8	106	November 20, 2022
[TableGen] Define single instruction allowing Reg/Imm operands or split to multiple instructions instead? Code Generation	6	250	November 17, 2022
Jump to Basic Block with only One Return Instruction Common Infrastructure	0	36	November 15, 2022
Steps to implement codegen for a new target (newbie question) Common Infrastructure	5	109	November 14, 2022
How could I tackle a simple "pass-through" code generator? Code Generation	3	69	November 9, 2022
CANCELLED RISC-V LLVM sync-up call 10th November 2022 RISCV	0	48	November 9, 2022
MachineSink sinking instructions beyond instructions with side effects? Code Generation	0	44	November 9, 2022
Optimising loops for simple consumers WebAssembly	2	114	November 9, 2022
Toolchain conventions: the -march string RISCV	0	70	November 8, 2022
Does it make sense for a function to have a personality/LSDA if it has no other unwind info? (Mach-O) Code Generation libunwind	4	189	November 7, 2022
Mismatch between DFA and Scoreboard Common Infrastructure	4	183	November 3, 2022
Initial patches for ARM64EC (Windows 11) now posted AArch64	6	604	November 3, 2022