Code Generation

Mips Ask questions about the Mips backend. PowerPC Discuss the PowerPC backend. X86 For questions about the X86 backend. ARM For questions about the Arm backend. AArch64 For questions about the AArch64 backend. AMDGPU This category is for discussions specific to both the development of the AMDGPU target in upstream LLVM and its use inside the LLVM project and by outside compiler frontends (e.g. LLPC, Mesa). RISCV For discussing RISCV code generation in LLVM. WebAssembly For questions about the WebAssembly backend. Common Infrastructure This category is for common code generation infrastructure related to all backends.

Topic	Replies	Views	Activity
About the Code Generation category Code Generation	4	316	January 11, 2022
Emission of CFI directives, CFI_remember_state and CFI_restore state in the epilogue for RISC-V RISCV	0	4	March 30, 2023
RISC-V LLVM sync-up call 30th March 2023 (note daylight savings time impact) RISCV	2	32	March 30, 2023
[RFC/PSA] Changing the shadow call stack register on RISC-V RISCV	3	140	March 30, 2023
Representing buffer descriptors in the AMDGPU target - call for suggestions AMDGPU	62	668	March 29, 2023
[RFC] Let MVT generated and restore MVT into llvm/CodeGen Common Infrastructure	0	47	March 27, 2023
Finding PC address of a given machine instruction Code Generation	4	76	March 27, 2023
[RFC] Let Intrinsics.td emit IIT_Info TypeSig Common Infrastructure	4	175	March 26, 2023
Building runtimes and builtins for RISC-V baremetal target (riscv64-unknown-elf) RISCV riscv , runtime , libcxx	3	113	March 23, 2023
RISC-V LLVM sync-up call 16th March 2023 (note daylight savings impact!) RISCV	0	71	March 15, 2023
GNU libgcrypt ATT asm style. Clang (llmv-as) doesn't pass autotool configure check unified asm code support ARM clang , llvm	2	140	March 15, 2023
Adding restrictions on target independent opcodes in MIR Code Generation llvm	5	192	March 15, 2023
[RFC] Resolving issues related to extension versioning in RISC-V RISCV	8	438	March 14, 2023
Folding memory into FMA X86	0	53	March 14, 2023
Understanding the impact of instruction scheduling for modern desctop CPUs Code Generation	5	178	March 10, 2023
Handling multiple exits in StructurizeCFG AMDGPU llvm	2	60	March 9, 2023
RFC: Machine Pipeliner interface Common Infrastructure	2	115	March 7, 2023
Save some bits in TSFlags for X86 X86 llvm	0	45	March 7, 2023
How to affect registers to make macro fusion happen Code Generation	2	62	March 7, 2023
Legalizing: integer promotion with custom expand Common Infrastructure	3	50	March 4, 2023
Tablegen: add custom field to Instruction description Common Infrastructure	2	52	March 3, 2023
Global ISel Common Infrastructure	7	158	March 3, 2023
Using MacOS calling convention to call external functions AArch64	4	90	March 2, 2023
Global Isel? RISCV	1	102	March 2, 2023
Running passes added by addPassesToEmitFile() mutates a module Common Infrastructure	2	54	March 2, 2023
RISC-V LLVM sync-up call 2nd March 2023 RISCV	0	95	March 1, 2023
SysV ABI non-power-of-two returns, motivation? X86	0	53	February 27, 2023
Handling PHIs in Uniformity Analysis AMDGPU	3	101	February 23, 2023
What do extra operands of COPY mean? Code Generation	4	90	February 22, 2023
Why is REG_SEQUENCE lowered during TwoAddressInstructions? Common Infrastructure	3	86	February 22, 2023