Code Generation

Mips Ask questions about the Mips backend. PowerPC Discuss the PowerPC backend. X86 For questions about the X86 backend. AArch64 For questions about the AArch64 backend. ARM For questions about the Arm backend. WebAssembly For questions about the WebAssembly backend. RISCV For discussing RISCV code generation in LLVM. AMDGPU This category is for discussions specific to both the development of the AMDGPU target in upstream LLVM and its use inside the LLVM project and by outside compiler frontends (e.g. LLPC, Mesa). Common Infrastructure This category is for common code generation infrastructure related to all backends.

Topic	Replies	Views	Activity
About the Code Generation category Code Generation	4	362	January 11, 2022
Exceptions and stack unwinding Common Infrastructure	0	31	May 27, 2023
Zmm and ymm register usage in llvm generated assembly Code Generation	1	62	May 27, 2023
Myterious soft-float output in LTO cache RISCV	15	197	May 27, 2023
LTO, ThinLTO, and Split DWARF Common Infrastructure thinlto , lto , llvm , debuginfo	0	46	May 26, 2023
Dead Code During Manual ISel Code Generation	2	50	May 26, 2023
[RFC] Renaming MachineInstr methods returning operand ranges Code Generation	16	153	May 25, 2023
RISC-V LLVM sync-up call May 25th 2023 RISCV	0	35	May 25, 2023
On vectorization under RISC-V and its existing interface to control scalable vectorization width - vectorize_width(VF, scalable) RISCV	13	581	May 25, 2023
CSRs defined in sstc extension RISCV llvm	0	20	May 24, 2023
Regarding ELFObjectemiter Code Generation llvm , clang	2	97	May 22, 2023
LLVM X86 backend asserts on a particular module and this reported bug isn't fixed for 8 + months X86	0	95	May 20, 2023
NVPTX problems with dynamic alloca Code Generation nvptx	1	52	May 19, 2023
Emission of CFI directives, CFI_remember_state and CFI_restore state in the epilogue for RISC-V RISCV	2	82	May 17, 2023
RFH: -global-isel-abort=1\|2 Common Infrastructure	5	97	May 16, 2023
Having the super-reg wrapper over the SPE registers in PPC Code Generation llvm	1	64	May 15, 2023
LR/SC atomic operations for A extension RISCV	4	70	May 15, 2023
RISCV Sign Extension Optimizations CorrelatedValuePropagation RISCV llvm , riscv , clang	1	59	May 15, 2023
[RFC] Prefix test invocations with the given tool for llvm-lit Common Infrastructure llvm	0	46	May 13, 2023
How to find an address of specific data section allocated by lljit? Code Generation	1	44	May 13, 2023
How to emit data to custom section Code Generation llvm	5	111	May 11, 2023
MemSDNode MultiMachineMemOperand Support(for async load store of gpu) Code Generation llvm	1	46	May 11, 2023
CANCELLED RISC-V LLVM sync-up call 11 May 2023 RISCV	0	63	May 10, 2023
Register alignment in RISCV RISCV	2	88	May 10, 2023
Problems with code model large and relocations AArch64	3	103	May 9, 2023
When There Are No Bytes Common Infrastructure	14	602	May 9, 2023
How to handle pointer relocation in LLVM? Common Infrastructure	0	55	May 6, 2023
"isolated" live interval segment with no defs in the predecessors: should the verifier have caught it? Code Generation regalloc , llvm	3	80	May 5, 2023
Is there any way to define custom calling convention without modifying llvm source code? Common Infrastructure	2	73	May 4, 2023
[RFC] Let MVT generated and restore MVT into llvm/CodeGen Common Infrastructure	3	338	May 4, 2023