Code Generation AMDGPU
| Topic | Replies | Views | Activity | |
|---|---|---|---|---|
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About the AMDGPU category
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4 | 499 | January 10, 2022 |
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Investigating high register pressure (at the IR level?)
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2 | 222 | April 11, 2023 |
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Representing buffer descriptors in the AMDGPU target - call for suggestions
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65 | 1322 | April 4, 2023 |
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Handling multiple exits in StructurizeCFG
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2 | 156 | March 9, 2023 |
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Handling PHIs in Uniformity Analysis
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3 | 249 | February 23, 2023 |
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[AMDGPU][LLC][LLVM] Cannot select: intrinsic %llvm.amdgcn.if
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0 | 296 | February 14, 2023 |
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Catching up on uniformity analysis
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5 | 248 | February 13, 2023 |
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Convert NVIDIA GPU LLVM IR(NVVM) alloca instruction to AMDGPU's
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7 | 618 | September 9, 2022 |
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[AMDGPU] Drop the GCNRegBankReassign pass
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1 | 325 | January 17, 2022 |
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GCNRegBankReassign pass issue
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0 | 345 | January 11, 2022 |
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The current state of spilling, function calls and related problems
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0 | 1429 | February 19, 2021 |