Topics tagged riscv

Topic	Replies	Views	Activity
How to get debug location at MCCodeEmitter when source file is a C file or bitcode file? RISCV riscv , debuginfo , llvm	0	10	September 21, 2023
Compile 128bit custom riscv instructions RISCV riscv , llvm	4	82	September 19, 2023
Break in gdb LLDB riscv , llvm	10	134	September 8, 2023
What does the set in the dag of the td file in tablegen refer to, (set a, b), where is the set defined? Beginners riscv , llvm	8	154	August 26, 2023
Is there any tablegen-related definition that provides this kind of function, which can complete the setting of DAG“Pat” “pattern” priority Beginners riscv , llvm	1	66	August 24, 2023
[RISCV][CLANG][CODEGEN] Possible bug in clang RISCV riscv , clang	5	198	August 22, 2023
Correct CMAKE parameters for building clang and lld for riscv LLVM Project riscv , cmake	2	116	August 17, 2023
When adding intrinsic in riscv，the command line option -target-feature fails to set the corresponding feature of subtarget to true, resulting in an error, so how to enable the feature correctly? Beginners riscv , clang , llvm	4	110	August 2, 2023
Create tablegen file of Q extension for RISCV LLVM Project riscv , llvm	0	87	July 22, 2023
Trapping math for RISC-V LLVM Project riscv , llvm	2	107	July 21, 2023
Inserting a created intrinsic function LLVM Dev List Archives riscv	0	146	July 20, 2023
Building and testing compiler-rt builtins for riscv64-unknown-elf CompilerRT riscv , runtime	2	120	July 20, 2023
What is the default rvv register bits length for code generation? How about the LMUL choice support status for rvv codegen in LLVM? RISCV riscv	5	198	July 17, 2023
Runtime-rt library build for RISCV Runtimes riscv	3	404	July 16, 2023
Adding a new instruction to RISC-V (starting from IR to binary) Beginners riscv , llvm	0	132	July 14, 2023
Clang_rt.crtbegin-riscv64.o: No such file or directory Building Clang riscv , clang , llvm	0	105	July 6, 2023
RISCV Clang cant find c++config.h Clang Frontend riscv , clang	1	139	July 6, 2023
Unable to build LLVM release/16.x on Ubuntu inside VirtualBox Beginners x86 , riscv , llvm	5	383	July 5, 2023
Unable to compile and run C/C++ program for RISC-V Beginners riscv , clang	5	298	June 20, 2023
What is PseudoVADD in RISC-V tablegen? RISCV riscv	1	191	June 19, 2023
Wrong RISCV assembly code for pseudo-LLA (Load Address) being generated since applying D99158.diff and D100288.diff patches RISCV riscv	3	190	June 16, 2023
RVV Vector Predication IR Lowering Question RISCV riscv	4	231	June 14, 2023
When I cross compile the MLIR, llvm-min-tblgen: Exec format error MLIR riscv	13	558	May 22, 2023
The latest version of llc generates an asm file that automatically adds zicsr2p0 to the .attribute Beginners riscv	14	204	May 18, 2023
Clang use ld default rather than use lld to link objects Beginners riscv	5	753	May 16, 2023
RISCV Sign Extension Optimizations CorrelatedValuePropagation RISCV riscv , clang , llvm	1	128	May 15, 2023
How to map a MachineInstr to multiple MCInst? Beginners riscv , llvm	5	155	May 8, 2023
IselDagtoDag Matching when an instruction updates more than one register [RISCV backend] Beginners riscv , llvm	2	135	May 3, 2023
Moving jump tables sections on embedded systems? Beginners riscv	0	220	April 26, 2023
Where can I find the code about the riscv auto vectorization part? Beginners riscv	2	168	April 26, 2023