Topics tagged riscv

Topic	Replies	Views	Activity
Merging RISCVToolChain and BareMetal toolchains Clang Frontend riscv , clang	5	455	December 5, 2024
What is the default rvv register bits length for code generation? How about the LMUL choice support status for rvv codegen in LLVM? RISCV riscv	8	702	December 5, 2024
Memref pass help MLIR gpu , riscv	5	56	November 18, 2024
How intelligent is LLVM backend? Common Infrastructure riscv , clang , llvm	6	139	November 7, 2024
Removing instructions from LLVM Compilation steps (without using Passes) RISCV riscv , clang , llvm	5	97	November 1, 2024
Support Instructions through instrinsic function in both riscv32 and riscv64 RISCV riscv	5	120	October 25, 2024
Shift instructions and avoiding poison Beginners riscv	1	70	September 23, 2024
Vscale multiplier set to 1 for any element type causes crash Code Generation riscv , llvm	3	57	September 12, 2024
[RFC] RISCV vector register spill optimization pass IR & Optimizations riscv , llvm	3	259	September 4, 2024
[RISCV] LTO for RISCV with gold linker RISCV riscv	4	96	August 26, 2024
Library/header include paths for barematel Clang Frontend riscv , clang , driver	2	58	August 20, 2024
How to optimize assembly emit for LLVM? LLVM Project riscv , llvm	5	128	August 16, 2024
Use the analysis of previous machine function pass Beginners riscv , llvm	4	56	August 7, 2024
Intrinsic lowered to pseudo not preserving glue Common Infrastructure riscv	3	51	July 26, 2024
Engaging more in a community Beginners riscv , llvm	1	124	July 23, 2024
How do I improve time and optimization quality in LLVM projects? Clang Frontend riscv , llvm	1	171	July 15, 2024
How to get RISCV instruction operand size RISCV riscv	5	150	July 5, 2024
Self build toolchains for RISC-V lacking correct libc Beginners riscv , libc	1	119	June 24, 2024
PromoteOperand error when adding intrinsics for custom RISC-V instruction Beginners riscv , llvm	1	102	June 17, 2024
Cross Compiling Using LLVM for Risc-v on x-86 machine Beginners riscv	3	209	June 17, 2024
Questions about the T-Head Vector extension (xtheadvector) in LLVM upstream LLVM Project riscv , llvm	14	471	June 14, 2024
Stack frame on RISC-V with RVE32 and +save-restore RISCV riscv	8	189	June 13, 2024
RISC-V default vs explicit ABI Using Clang riscv	0	92	June 12, 2024
Error encountered while compiling clang and OpenMP for RISC-V target LLVM Project riscv , llvm	9	214	June 7, 2024
How to build compiler-rt with -march and -mabi CompilerRT riscv	2	97	June 7, 2024
Software Engineer (Compilers & Virtual Machines) @ Parity \| Polkadot Job Postings riscv , llvm	0	304	June 5, 2024
Compile compiler-rt for riscv with dedicated library name Beginners riscv , clang	7	211	June 4, 2024
RISC V RVV fine-grained LMUL settings RISCV riscv , clang	1	138	May 31, 2024
Which pass inserts vector instruction (RVV) for memory move/copy operations? RISCV riscv , clang	1	112	May 31, 2024
How can i make "exe" files in ubuntu Beginners riscv , clang , llvm	0	89	May 16, 2024