How to get debug location at MCCodeEmitter when source file is a C file or bitcode file?
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0
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10
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September 21, 2023
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Compile 128bit custom riscv instructions
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4
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82
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September 19, 2023
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Break in gdb
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10
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134
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September 8, 2023
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What does the set in the dag of the td file in tablegen refer to, (set a, b), where is the set defined?
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8
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154
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August 26, 2023
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Is there any tablegen-related definition that provides this kind of function, which can complete the setting of DAG“Pat” “pattern” priority
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1
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66
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August 24, 2023
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[RISCV][CLANG][CODEGEN] Possible bug in clang
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5
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198
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August 22, 2023
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Correct CMAKE parameters for building clang and lld for riscv
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2
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116
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August 17, 2023
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When adding intrinsic in riscv,the command line option -target-feature fails to set the corresponding feature of subtarget to true, resulting in an error, so how to enable the feature correctly?
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4
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110
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August 2, 2023
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Create tablegen file of Q extension for RISCV
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0
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87
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July 22, 2023
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Trapping math for RISC-V
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2
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107
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July 21, 2023
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Inserting a created intrinsic function
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0
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146
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July 20, 2023
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Building and testing compiler-rt builtins for riscv64-unknown-elf
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2
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120
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July 20, 2023
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What is the default rvv register bits length for code generation? How about the LMUL choice support status for rvv codegen in LLVM?
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5
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198
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July 17, 2023
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Runtime-rt library build for RISCV
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3
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404
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July 16, 2023
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Adding a new instruction to RISC-V (starting from IR to binary)
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0
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132
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July 14, 2023
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Clang_rt.crtbegin-riscv64.o: No such file or directory
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0
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105
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July 6, 2023
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RISCV Clang cant find c++config.h
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1
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139
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July 6, 2023
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Unable to build LLVM release/16.x on Ubuntu inside VirtualBox
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5
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383
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July 5, 2023
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Unable to compile and run C/C++ program for RISC-V
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5
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298
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June 20, 2023
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What is PseudoVADD in RISC-V tablegen?
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1
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191
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June 19, 2023
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Wrong RISCV assembly code for pseudo-LLA (Load Address) being generated since applying D99158.diff and D100288.diff patches
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3
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190
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June 16, 2023
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RVV Vector Predication IR Lowering Question
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4
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231
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June 14, 2023
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When I cross compile the MLIR, llvm-min-tblgen: Exec format error
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13
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558
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May 22, 2023
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The latest version of llc generates an asm file that automatically adds zicsr2p0 to the .attribute
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14
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204
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May 18, 2023
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Clang use ld default rather than use lld to link objects
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5
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753
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May 16, 2023
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RISCV Sign Extension Optimizations CorrelatedValuePropagation
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1
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128
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May 15, 2023
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How to map a MachineInstr to multiple MCInst?
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5
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155
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May 8, 2023
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IselDagtoDag Matching when an instruction updates more than one register [RISCV backend]
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2
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135
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May 3, 2023
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Moving jump tables sections on embedded systems?
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0
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220
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April 26, 2023
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Where can I find the code about the riscv auto vectorization part?
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2
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168
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April 26, 2023
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