Topics tagged riscv

Topic	Replies	Views	Activity
Recommended open-source 32-bit RISC-V core for validating custom LLVM backend extensions? RISCV riscv , llvm	1	54	May 26, 2025
Creating SHF_MERGE\|SHF_STRINGS section Using Clang riscv	3	97	May 22, 2025
[RFC] New analysis for Polynomial Hash recognition Loop Optimizations riscv , llvm	2	206	May 10, 2025
Help with Segmentation Fault from Custom Pseudo-Instruction Optimization on RISC-V(Xalancbmk)) RISCV riscv , clang , llvm	6	81	May 9, 2025
Implicit conversion between RVV types and vector_size types with -mrvv-vector-bits=scalable Clang Frontend riscv	2	39	April 23, 2025
Inquiry about the latest way to enable auto-vectorization for RVV RISCV riscv	4	107	April 7, 2025
LLDB disassembly of RISC-V extension instructions LLDB riscv	8	63	March 25, 2025
[Notification] HelloLLVM Community Meetup on March 22, 2025 Announcements riscv , llvm	0	143	March 17, 2025
How to define builtins functions that use my builtin types Clang Frontend riscv	6	79	March 11, 2025
Why is the relocation function the same for R_RISCV_HI20 and R_RISCV_PCREL_HI20? LLD riscv	2	57	March 11, 2025
Senior Developer for Compilers and Static Analysis @ Samsung Research Poland Job Postings x86 , arm , riscv , clang , llvm	0	147	February 12, 2025
Discrepancy of `long int` between llvm and gcc in riscv32 Using Clang riscv	8	100	February 11, 2025
Help Needed: Handling Redundant Instructions in RISC-V Backend DAG->DAG Pattern Selection RISCV riscv , llvm	3	57	January 28, 2025
Lowering LLVM vector types in RISC-V RISCV riscv , llvm	2	64	January 28, 2025
How to link .o files with clang? Beginners riscv , clang , llvm	9	134	January 28, 2025
Scalable vector types in clang builtins using `TargetBuiltin` Clang Frontend riscv , clang	1	32	January 16, 2025
Why are the branch instructions not ```isBarrier = 1``` RISCV riscv	2	63	January 8, 2025
Question about rv32imfc march and double operation insertion Beginners riscv , clang , llvm	1	43	January 6, 2025
Maybe we need optimize READ_REGISTER AND WRITE_REGISTER RISCV riscv	7	136	December 31, 2024
Inquiry About mlir-cpu-runner Support for RISC-V Platform MLIR riscv , mlir	3	95	December 29, 2024
[RISCV] Do we need to change the default configuration to rva23u64 RISCV riscv	2	147	December 12, 2024
Merging RISCVToolChain and BareMetal toolchains Clang Frontend riscv , clang	5	522	December 5, 2024
What is the default rvv register bits length for code generation? How about the LMUL choice support status for rvv codegen in LLVM? RISCV riscv	8	726	December 5, 2024
Memref pass help MLIR gpu , riscv	5	74	November 18, 2024
How intelligent is LLVM backend? Common CodeGen Infrastructure riscv , clang , llvm	6	168	November 7, 2024
Removing instructions from LLVM Compilation steps (without using Passes) RISCV riscv , clang , llvm	5	114	November 1, 2024
Support Instructions through instrinsic function in both riscv32 and riscv64 RISCV riscv	5	134	October 25, 2024
Shift instructions and avoiding poison Beginners riscv	1	73	September 23, 2024
Vscale multiplier set to 1 for any element type causes crash Code Generation riscv , llvm	3	63	September 12, 2024
[RFC] RISCV vector register spill optimization pass IR & Optimizations riscv , llvm	3	288	September 4, 2024