|
About the RISCV category
|
|
0
|
322
|
January 8, 2022
|
|
Generating RISCV code from MLIR
|
|
10
|
122
|
April 18, 2025
|
|
How is the size of the shamt checked for SLL?
|
|
2
|
34
|
April 11, 2025
|
|
Inquiry about the correct support for vfma
|
|
2
|
40
|
April 10, 2025
|
|
Is anyone else seeing an error in spec2k6 445.gobmk using just scalar?
|
|
4
|
85
|
April 9, 2025
|
|
CANCELLED RISC-V LLVM sync-up call April 10th 2025
|
|
0
|
23
|
April 9, 2025
|
|
Inquiry about the latest way to enable auto-vectorization for RVV
|
|
4
|
88
|
April 7, 2025
|
|
Get wrong result when building undefined type conversion source code
|
|
3
|
32
|
April 3, 2025
|
|
RISC-V LLVM sync-up call March 27th 2025 *NOTE DAYLIGHT SAVINGS IMPACT*
|
|
0
|
33
|
March 26, 2025
|
|
Question on getting vector size in tablegen?
|
|
5
|
58
|
March 21, 2025
|
|
RISC-V LLVM sync-up call March 13th 2025 *NOTE DAYLIGHT SAVINGS IMPACT*
|
|
0
|
38
|
March 12, 2025
|
|
RISC-V LLVM sync-up call February 27th 2025
|
|
0
|
32
|
February 27, 2025
|
|
RISC-V LLVM sync-up call February 13th 2025
|
|
2
|
51
|
February 27, 2025
|
|
Why is Return address X1 defined as Callee Saved Register
|
|
3
|
81
|
February 25, 2025
|
|
DeadLaneDetector problem after instruction selection
|
|
8
|
87
|
February 21, 2025
|
|
RISC-V LLVM sync-up call January 30th 2025
|
|
0
|
31
|
January 29, 2025
|
|
Help Needed: Handling Redundant Instructions in RISC-V Backend DAG->DAG Pattern Selection
|
|
3
|
54
|
January 28, 2025
|
|
Lowering LLVM vector types in RISC-V
|
|
2
|
61
|
January 28, 2025
|
|
RISC-V LLVM sync-up call January 16th 2025
|
|
0
|
48
|
January 15, 2025
|
|
Does RISCV RVV has any C++ syntax to create vector
|
|
1
|
65
|
January 9, 2025
|
|
Why are the branch instructions not ```isBarrier = 1```
|
|
2
|
60
|
January 8, 2025
|
|
Maybe we need optimize READ_REGISTER AND WRITE_REGISTER
|
|
7
|
135
|
December 31, 2024
|
|
RISC-V LLVM sync-up call December 19th 2024
|
|
0
|
65
|
December 17, 2024
|
|
Patterns for SDNode and RISCV instruction with no result/output
|
|
5
|
80
|
December 12, 2024
|
|
[RISCV] Do we need to change the default configuration to rva23u64
|
|
2
|
144
|
December 12, 2024
|
|
FFT algorithms in RISC-V Vector Extensons
|
|
0
|
56
|
December 10, 2024
|
|
[RFC][RISC-V] Add support for MIPS P8700 CPU
|
|
2
|
236
|
November 29, 2024
|
|
Fixed Register Being Spill and Restored in Clang
|
|
11
|
176
|
December 6, 2024
|
|
RISC-V LLVM sync-up call December 5th 2024
|
|
0
|
34
|
December 4, 2024
|
|
What is the default rvv register bits length for code generation? How about the LMUL choice support status for rvv codegen in LLVM?
|
|
8
|
719
|
December 5, 2024
|