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About the Common CodeGen Infrastructure category
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0
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325
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January 8, 2022
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MachineScheduler: why does the heuristic unconditionally relax the pressure limit by LiveThru?
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2
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125
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October 16, 2026
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[RFC] Add widening multiply libcalls to RuntimeLibcalls
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4
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164
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October 16, 2026
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[RFC] Respecting freeze semantics in backends
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22
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671
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October 11, 2026
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Memory Corruption in LLVM
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3
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268
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October 2, 2026
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Beginner guide for LLVM backend development for AArch64
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3
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292
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September 21, 2026
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[RFC] Exposing Pre-RA Scheduling for Search and ML Experimentation
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8
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342
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September 11, 2026
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Shrink Wrap Save/Restore Points Splitting
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26
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1925
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August 25, 2026
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Error in backend: Can't handle live physical register dependency!
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3
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244
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July 30, 2026
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How to define multiple RegisterTuples for the same registers?
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2
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165
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July 22, 2026
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[RFC] Improving LLVM Support for Alternative Constraints in GNU Extended Inline Assembly
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25
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1033
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July 15, 2026
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Dropping intrinsic arguments in tblgen (solved)
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3
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191
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July 14, 2026
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[RFC] MachineLaneSSAUpdater — target-independent SSA repair with subregister lane awareness for Machine IR
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5
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274
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July 1, 2026
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[CSSPGO] Callsite pseudo-probe type bit becomes stale after IR devirtualization
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7
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319
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May 30, 2026
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[CodeGen] Completing the SplitKit subrange mismatch fix from D88020
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4
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214
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May 2, 2026
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A subregister of wide register class needs spill, but regalloc spills this wide register, how to opt it?
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3
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220
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April 28, 2026
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[RFC] Out of LaneBitMask Bits Again
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11
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922
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March 30, 2026
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[RFC][DwarfDebug] Fix and improve handling imported entities, types and static local in subprogram and lexical block scopes
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14
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1662
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March 4, 2026
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About inline asm instruction order
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6
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343
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February 28, 2026
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Padding for minimum function size
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5
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290
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February 3, 2026
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Can min/max operation with same values combined?
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1
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132
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December 23, 2025
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Running out of bits in TSFlags
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3
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226
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December 4, 2025
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Memory Prefetching Support in LLVM
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12
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2157
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November 10, 2025
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Encoding of explicit parallel instructions
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4
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285
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October 27, 2025
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RFC: Generic DAG nodes for floating-point operations
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5
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378
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October 17, 2025
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PSA: New flag to dump SelectionDAG with sorted SDNode
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0
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113
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October 6, 2025
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Patterns not appearing in the GenDAGISel.inc
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5
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243
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September 30, 2025
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[RFC][GlobalISel] Adding FP type information to LLT
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40
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2023
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September 11, 2025
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Does synthetic IR like massive_N1e6.ll have value for testing register allocation performance?
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2
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175
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September 8, 2025
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[tblgen] Rewriting of a result instruction DAG node for InstAlias
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8
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286
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August 27, 2025
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