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About the Common CodeGen Infrastructure category
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0
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256
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January 8, 2022
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[RFC][DwarfDebug] Fix and improve handling imported entities, types and static local in subprogram and lexical block scopes
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11
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910
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May 28, 2025
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Match DAG node with 2 results
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1
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61
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May 20, 2025
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New llvm Intrinsic
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0
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52
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May 7, 2025
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Tail merge vs. bundles
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9
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155
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May 4, 2025
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How do I get the future index of a symbol in the AsmPrinter stage?
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4
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102
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April 29, 2025
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Reassociating Expressions with Memory Operands to increase ILP for X86 Targets
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0
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27
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April 28, 2025
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Improving pre-RA MachineScheduler
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1
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110
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April 25, 2025
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[RFC] ExpandMemCmpPass is not prepared for architectures smaller than 32 bit
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1
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34
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April 22, 2025
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Instrumenting code after register allocation for ARM backends
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0
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35
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April 18, 2025
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SDAG Node morphed incorrectly during Instruction Selection
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5
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76
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April 14, 2025
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[RFC] Codegen new pass manager pipeline construction design
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4
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533
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April 6, 2025
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Map from MachineOperand to SlotIndex and vice versa
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2
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34
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April 9, 2025
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Shrink Wrap Save/Restore Points Splitting
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14
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469
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March 31, 2025
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MIR verification rule banning unconnected components
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1
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34
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March 30, 2025
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Can a normal compiler include a MachineFunctionPass?
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4
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300
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March 29, 2025
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Why does IRTranslator align the size for dynamic alloca?
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4
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111
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March 19, 2025
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[RFC][LLVM] Add Support for Target Specific Asm Streamer
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0
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34
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March 10, 2025
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Any users of getLogicalOperandType GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP?
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4
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37
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February 10, 2025
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PSA: API breaking changes for named operands in MIR
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0
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68
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February 6, 2025
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Question about RuntimeDyld::MemoryManager::allowStubAllocation
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0
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10
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February 3, 2025
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SelectionDAG: Why there are no special cases handled in haveNoCommonBitsSet() implemented?
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2
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60
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January 31, 2025
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Newbie how to prevent constant:i32<2> from becoming i8=constant<2>
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2
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51
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January 29, 2025
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Using CodeGen information to modify IR
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2
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57
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January 17, 2025
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Can't fold LOAD into user during ISel
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16
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169
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January 10, 2025
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How do I get desired 'align' for byVal passes of struct vars to procedure calls in IR code? Where should I look to configure that?
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0
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20
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January 7, 2025
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I want to default to ZEXT Loads instead of SEXT on my custom backend. Where should I look to change that?
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5
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93
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January 5, 2025
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[RFC][GlobalISel] Adding FP type information to LLT
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36
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591
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December 13, 2024
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Confusion about PostRAScheduler
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0
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56
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December 6, 2024
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Why was post-misched originally designed with only a TopDown direction?
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7
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164
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November 20, 2024
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