|
Code generation for llvm-mca instrumentation
|
|
9
|
162
|
October 25, 2022
|
|
Is it possible to disable a specific instruction in AArch64?
|
|
2
|
93
|
October 19, 2022
|
|
[RFC] Restrict read only when cache type of llvm.prefetch is instruction
|
|
0
|
48
|
October 18, 2022
|
|
Auto-generate the memory folding tables
|
|
29
|
515
|
October 18, 2022
|
|
Unordered Floating Noint Numbers (and Infinite ones too)
|
|
11
|
136
|
October 17, 2022
|
|
TableGen: Subtargets with different encodings
|
|
5
|
140
|
October 13, 2022
|
|
CANCELLED RISC-V LLVM sync-up call 13th October 2022
|
|
0
|
68
|
October 13, 2022
|
|
Generating control flow with multiple return destinations
|
|
2
|
72
|
October 11, 2022
|
|
How to build compiler-rt for new X86 half float ABI
|
|
25
|
750
|
October 10, 2022
|
|
Proposed change to X86 Code Ownership
|
|
9
|
383
|
October 9, 2022
|
|
Managing MCInstrPrinter and Including GenRegisterInfo.inc; small backend guide
|
|
14
|
218
|
October 8, 2022
|
|
Use of callbr for non-asm goto
|
|
3
|
96
|
October 7, 2022
|
|
Using MCAsmParser to generate MCInst
|
|
2
|
80
|
October 7, 2022
|
|
X86InstrInfo
|
|
1
|
63
|
October 7, 2022
|
|
Ifcvt: Detecting predicate cloober in GPRs
|
|
0
|
52
|
October 6, 2022
|
|
ThinLTO does not account for mangle-suppression prefix (Mach-O issue)
|
|
1
|
97
|
October 3, 2022
|
|
RISC-V V C Intrinsic API v1.0 release meeting reminder (Oct 03, 2022)
|
|
1
|
73
|
October 3, 2022
|
|
RISC-V LLVM sync-up call 29th September 2022
|
|
2
|
99
|
September 29, 2022
|
|
Instruction Set Randomization
|
|
0
|
58
|
September 25, 2022
|
|
Risc-V pointer masking extension support in llvm
|
|
1
|
108
|
September 24, 2022
|
|
Does `isless` trap on signaling NaN?
|
|
2
|
121
|
September 23, 2022
|
|
[RFC] Syncing Asm Goto with Outputs with GCC
|
|
3
|
199
|
September 22, 2022
|
|
[RFC] Tensilica Xtensa (ESP32) backend
|
|
8
|
939
|
September 20, 2022
|
|
Supporting macro-fusion on X86
|
|
1
|
121
|
September 20, 2022
|
|
How does SDUse work?
|
|
0
|
62
|
September 16, 2022
|
|
How to replace member of instructions in different SubtargetFeature
|
|
3
|
90
|
September 16, 2022
|
|
Mips's i64 shift int lowerShiftRightParts?
|
|
1
|
72
|
September 15, 2022
|
|
RISC-V LLVM sync-up call 15th September 2022
|
|
0
|
85
|
September 14, 2022
|
|
General question about variable type of operand in add operation
|
|
1
|
82
|
September 13, 2022
|
|
LLVM intrinsic functions
|
|
11
|
237
|
September 13, 2022
|