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How to add a customed argument in llc?
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1
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48
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February 16, 2023
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RISC-V LLVM sync-up call 16th February 2023
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0
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90
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February 15, 2023
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Is there any way to run a pass before AsmPrinter?
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2
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71
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February 15, 2023
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[AMDGPU][LLC][LLVM] Cannot select: intrinsic %llvm.amdgcn.if
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0
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86
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February 14, 2023
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Support for "zicsr" and "zifencei" extensions
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5
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140
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February 13, 2023
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Is lldb for riscv ready to use?
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3
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177
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February 13, 2023
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Catching up on uniformity analysis
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5
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116
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February 13, 2023
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Why do sub-byte loads on AArch64 not require masking?
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11
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179
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February 11, 2023
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Question about register spilling, rematerialization, and racy accesses
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3
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141
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February 10, 2023
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Resource MII computation in MachinePipeliner
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1
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79
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February 10, 2023
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Changes to MCInstrDesc and tablegenned instruction tables (was Re: Impact of default PIE on llvm testing times)
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3
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153
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February 10, 2023
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Lld link newlib nano show out of range error for _printf_float
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0
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49
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February 10, 2023
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Link failed using riscv clang for rv64imac arch
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7
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103
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February 10, 2023
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Is anyone able to build libcxx/libcxxabi for riscv
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0
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43
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February 9, 2023
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ELF mergeable sections
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4
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95
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February 9, 2023
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`llvm.vp.*` mask semantics not being honored when targeting x86?
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3
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67
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February 2, 2023
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What is the correct sequence of IR instructions to generate subs+sbc pair?
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2
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78
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February 2, 2023
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Pointer-typed globals in larger-than-pointer integer containers fails
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6
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104
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February 1, 2023
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RISC-V LLVM sync-up call 2nd February 2023
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0
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92
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February 1, 2023
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Inlining mathematical function
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0
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149
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January 30, 2023
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128 bit shifts constants expanded when shift parts is legal
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6
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96
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January 26, 2023
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Regarding ELF_RELOC
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2
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75
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January 26, 2023
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Initial patches for ARM64EC (Windows 11) now posted
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8
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853
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January 25, 2023
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Does anyone use llvm-exegesis? Feedback wanted
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18
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348
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January 20, 2023
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CANCELLED RISC-V LLVM sync-up call 19th January 2023
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0
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64
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January 19, 2023
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What's RegState usage?
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3
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126
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January 12, 2023
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Memory dependence around read-modify-write instructions
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2
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87
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January 12, 2023
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Has anyone tried Cpu0 code with the recent llvm (llvm 14 or up)?
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0
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79
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January 11, 2023
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Generating x86 instruction prefixes in a MachineInstr for lowering
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1
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88
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January 10, 2023
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Questions about DAG.getMemIntrinsicNode
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2
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76
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January 10, 2023
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