Code Generation

Topic	Replies	Views	Activity
[RISCV][CLANG][CODEGEN] Possible bug in clang RISCV riscv , clang	5	202	August 22, 2023
[GlobalISel] using low-level type s0 as an opaque token type Code Generation globalisel	0	111	August 22, 2023
How to generate disassembly of ORC JIT Code Generation llvm	1	81	August 22, 2023
Correct behavior for preservation of x87/MMX state in interrupt handler X86 clang , llvm	0	45	August 21, 2023
Is this a bug? "+multivalue" attribute contaminates non-multivalue functions WebAssembly webassembly , llvm , llvm-ir	5	125	August 21, 2023
Arm neon ldrb before st2 error lead to compare fail Code Generation arm64 , clang , llvm	1	55	August 16, 2023
RISC-V LLVM sync-up call August 17th 2023 RISCV	0	63	August 16, 2023
How dose Sched<[WriteVFMovV_UpperBound, ReadVFMovF_UpperBound]> work? RISCV	2	78	August 16, 2023
[clang]Assigning an uninitialized array to another array produces undefined behavior with optimization -O1 Code Generation clang , llvm	2	123	August 15, 2023
[bug][clang] with optimization -O1 will get wrong result Code Generation clang , llvm	5	139	August 14, 2023
[bug][arm64be] #pragma pack(1) and volatile keyword will get wrong result Code Generation clang , llvm	0	86	August 10, 2023
[bug][arm64be]with the optimize option -O3 and volatile keyword will get wrong result Code Generation clang , llvm	0	61	August 8, 2023
Add custom executable (output object) format Code Generation	10	809	August 7, 2023
Replacing instruction with multiple substitute instructions RISCV	2	81	August 6, 2023
Why don't we define RISCV calling conventions in TableGen way just like other targets? RISCV	11	223	August 4, 2023
[MachineLICM] Should we set RegLimit using RegisterClassInfo::getRegPressureSetLimit()? Common Infrastructure	0	70	August 4, 2023
[RFC] Assembly Super Optimiser Code Generation	19	1620	August 4, 2023
RISC-V LLVM sync-up call August 3rd 2023 RISCV	0	72	August 3, 2023
ILP32 support with Aarch64 AArch64 clang	6	234	August 2, 2023
Is it possible to use the result of an IR analysis pass in a MIR pass? Common Infrastructure llvm	2	84	August 2, 2023
[AArch64] Improve vector multiply by constant #54651 AArch64	0	58	July 31, 2023
MemSDNode MultiMachineMemOperand Support(for async load store of gpu) Code Generation llvm	3	122	July 29, 2023
AArch64_be generate diff code for int8_t with AArch64_le? AArch64 clang , llvm	12	217	July 28, 2023
MachineScheduler: Latency of edges to call schedule boundary Common Infrastructure	0	91	July 25, 2023
SUBREG_TO_REG semantics (or x86's zext implementation is broken) Code Generation x86	9	176	July 26, 2023
[RFC] Overhauled MIR Patterns for GlobalISel Combiners Code Generation globalisel	1	241	July 26, 2023
RISC-V LLVM sync-up call July 20th 2023 RISCV	0	93	July 20, 2023
Global TLS var CodenGen error in Aarch64 AArch64 clang	2	142	July 19, 2023
[RFC] MatchTable-based GlobalISel Combiners Common Infrastructure globalisel , llvm	12	732	July 19, 2023
How to make my target output XCOFF? Common Infrastructure	1	87	July 19, 2023