[RISCV][CLANG][CODEGEN] Possible bug in clang
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5
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202
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August 22, 2023
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[GlobalISel] using low-level type s0 as an opaque token type
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0
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111
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August 22, 2023
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How to generate disassembly of ORC JIT
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1
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81
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August 22, 2023
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Correct behavior for preservation of x87/MMX state in interrupt handler
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0
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45
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August 21, 2023
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Is this a bug? "+multivalue" attribute contaminates non-multivalue functions
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5
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125
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August 21, 2023
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Arm neon ldrb before st2 error lead to compare fail
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1
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55
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August 16, 2023
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RISC-V LLVM sync-up call August 17th 2023
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0
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63
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August 16, 2023
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How dose Sched<[WriteVFMovV_UpperBound, ReadVFMovF_UpperBound]> work?
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2
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78
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August 16, 2023
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[clang]Assigning an uninitialized array to another array produces undefined behavior with optimization -O1
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2
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123
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August 15, 2023
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[bug][clang] with optimization -O1 will get wrong result
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5
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139
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August 14, 2023
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[bug][arm64be] #pragma pack(1) and volatile keyword will get wrong result
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0
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86
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August 10, 2023
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[bug][arm64be]with the optimize option -O3 and volatile keyword will get wrong result
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0
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61
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August 8, 2023
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Add custom executable (output object) format
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10
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809
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August 7, 2023
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Replacing instruction with multiple substitute instructions
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2
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81
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August 6, 2023
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Why don't we define RISCV calling conventions in TableGen way just like other targets?
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11
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223
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August 4, 2023
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[MachineLICM] Should we set RegLimit using RegisterClassInfo::getRegPressureSetLimit()?
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0
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70
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August 4, 2023
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[RFC] Assembly Super Optimiser
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19
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1620
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August 4, 2023
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RISC-V LLVM sync-up call August 3rd 2023
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0
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72
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August 3, 2023
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ILP32 support with Aarch64
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6
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234
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August 2, 2023
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Is it possible to use the result of an IR analysis pass in a MIR pass?
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2
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84
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August 2, 2023
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[AArch64] Improve vector multiply by constant #54651
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0
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58
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July 31, 2023
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MemSDNode MultiMachineMemOperand Support(for async load store of gpu)
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3
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122
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July 29, 2023
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AArch64_be generate diff code for int8_t with AArch64_le?
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12
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217
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July 28, 2023
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MachineScheduler: Latency of edges to call schedule boundary
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0
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91
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July 25, 2023
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SUBREG_TO_REG semantics (or x86's zext implementation is broken)
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9
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176
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July 26, 2023
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[RFC] Overhauled MIR Patterns for GlobalISel Combiners
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1
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241
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July 26, 2023
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RISC-V LLVM sync-up call July 20th 2023
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0
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93
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July 20, 2023
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Global TLS var CodenGen error in Aarch64
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2
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142
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July 19, 2023
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[RFC] MatchTable-based GlobalISel Combiners
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12
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732
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July 19, 2023
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How to make my target output XCOFF?
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1
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87
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July 19, 2023
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