Add RISC-V CSRs to core dumps

Subprojects LLDB
6

Hi, David,

We’ve added support for facilitating postmortem debug of 32-bit RISC-V core dump images downstream, and are planning to upstream it in multiple phases –

  • The first phase will add general support for facilitating postmortem debug of 32-bit RISC-V core dump images

  • The second phase will add support for handling subsets of CSRs in 32-bit RISC-V core dump images

We will put these up for review immediately.

  • The third phase will add support for updating the register information for CSRs specified by custom extensions dynamically since CSRs specified by a custom extension could overlap with those specified by another custom extension

  • The fourth phase will switch to dynamic register information in the support for facilitating postmortem debug of 64-bit RISC-V core dump images; additionally, it will add support for handling subsets of CSRs in 64-bit RISC-V core dump images

These are under development and will be put up for review soon.

Does this sound good to you?

Thanks, and best regards,
Ayush