HW dialect support for parameterizable module

Hi everybody! I’m currentling trying to express the parameter semantics using hw dialect when defining a module in SystemVerilog like this:

module foo
#( bitwidth = 32 )
  input [bitwidth-1:0] i,
  output [bitwidth-1:0] o

I see there are some examples of !hw.int type in test/Conversion/ExportVerilog/hw-dialect.mlir such as this:

hw.module @parameters3<p1: i42 = 17>(in %arg0: !hw.int<#hw.param.decl.ref<"p1">>, out out: !hw.int<#hw.param.decl.ref<"p1">>) {
  hw.output %arg0 : !hw.int<#hw.param.decl.ref<"p1">>

But when I try to use --export-verilog, it reports this error in the stack tree:

/circt/lib/Dialect/Handshake/Transforms/PassHelpers.cpp:96: mlir::LogicalResult circt::handshake::resolveInstanceGraph(mlir::ModuleOp, circt::handshake::InstanceGraph &, std::string &, SmallVectorImpl<std::string> &): Assertion `!candidateTopLevel.empty() && "if non-cyclic, there should be at least 1 candidate top level"' failed.

Anyone has idea why?

Okay, nvmd, I messed up with CIRCT version and stuffs. It works perfectly now :joy: