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About the CIRCT category
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0
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1159
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August 21, 2020
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CIRCT ECO in the presence of transformations
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7
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74
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March 22, 2023
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Is CIRCT able to analyze Verilog
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12
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388
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March 21, 2023
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Firtool - removing unused definitions from every .sv file
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1
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36
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March 20, 2023
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[RFC] Split Pipeline Dialect and Add Representation for Sequential Loop Scheduling
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4
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115
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March 20, 2023
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Problems with Verilator linting warning in Chisel generated code
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0
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39
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March 14, 2023
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Exported Calyx doesn't add memory
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6
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86
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March 2, 2023
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Pass Failed: AffineToPipeline
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23
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206
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February 23, 2023
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Call for ODM Talks - LEC, Simulation, Synthesis, Vendor-specific dialect(s)/outputs
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4
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120
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February 10, 2023
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Integrate logic synthesis and optimisation capabilities
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8
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269
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January 31, 2023
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New to CIRCT; Is there example using CIRCT to FIRRTL-to-ASAP7 synthesis?
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1
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157
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January 31, 2023
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3rd Workshop on Languages, Tools, and Techniques for Accelerator Design
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0
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73
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January 24, 2023
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CIRCT Bay Area Meetup 11/8/22
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5
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244
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November 9, 2022
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Is there a circt tutorial which shows scheduling capabilities of the tool?
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1
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208
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November 1, 2022
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How to disable Randomize in Firtool generated SV
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1
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148
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October 31, 2022
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Took chisel-circt 0.6.0 and LLVM 1.15.0 for a spin
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3
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181
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October 28, 2022
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Is there an op in the calyx dialect that maps invoke?
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6
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157
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October 20, 2022
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Is there some way to run the calyx dialect
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2
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123
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October 19, 2022
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Integration with ABC optimizer
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3
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334
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October 17, 2022
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Firtool fails on chisel-circt-demo
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4
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220
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September 28, 2022
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Circt-opt gives error for the input mlir (in core dialects) - which was generated by the firtool from the .fir file corresponding to the standard GCD tester
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2
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93
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September 21, 2022
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Is it feasible to convert "pipeline" dialect" to "FSM" directly?
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3
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152
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September 14, 2022
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WOSET'22 call for papers
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1
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220
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September 9, 2022
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Latency-Insensitive Finite State Machine
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4
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194
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August 30, 2022
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[ESI (ostensibly)] On memory services/streams
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1
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161
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August 23, 2022
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CIRCT now in Compiler Explorer (godbolt.org)
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2
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478
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August 4, 2022
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LLVM / Pull request discussion
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0
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185
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July 21, 2022
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Lack of constructs with a sensitivity list
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10
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214
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July 16, 2022
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FPGA development for a newbie?
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3
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394
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July 7, 2022
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[RFC] Representing pipelined loops
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31
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1104
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July 7, 2022
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