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About the CIRCT category
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0
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1376
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August 21, 2020
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Help debugging CIRCT - LLDB doesn't find half the names
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2
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44
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September 20, 2023
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Handshake FuncOp creation
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1
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55
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September 15, 2023
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Error: unknown type `clock` in dialect `seq`
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2
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55
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September 14, 2023
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Firtool creates empty .sv files when it is passed "-o=."
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3
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49
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September 10, 2023
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Firtool - how do I remove the header?
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1
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43
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September 8, 2023
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Lowering to FIRRTL dialect: lowering to FModuleOp from an Op that does not have clock and reset ports
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2
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49
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September 7, 2023
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Lowering to FIRRTL dialect
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2
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55
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September 5, 2023
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[Firtool] chisel for loop to verilog
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3
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66
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September 1, 2023
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Problematic behavior of pass --convert-affine-to-loopschedule
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11
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131
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August 31, 2023
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Potential bug in CombToArith Pass?
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2
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39
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August 31, 2023
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-convert-fsm-to-sv Pass Fail
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4
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112
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July 31, 2023
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Firtool - removing unused definitions from every .sv file
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3
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219
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July 24, 2023
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Target Triples for Hardware Compilers
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7
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720
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July 21, 2023
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FIFO channel in CIRCT
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13
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315
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July 20, 2023
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Sv.reg names
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4
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112
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July 13, 2023
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[CIRCTHLS]-Hlstool Lowering Problems
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0
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99
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July 10, 2023
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Is CIRCT able to analyze Verilog
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26
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1363
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July 9, 2023
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[Question] Handshake dialect doc
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2
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100
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July 4, 2023
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Sv.wire and hw.wire
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2
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110
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June 22, 2023
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C++ or RUST to VHDL
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3
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334
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June 10, 2023
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CIRCT install not working
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2
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115
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June 10, 2023
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Some question about fsm dialect?
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3
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137
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June 8, 2023
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How to show the generic form for ops in CIRCT dialects
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1
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136
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May 12, 2023
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How to compile chisel to HW?
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2
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200
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May 9, 2023
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Should SSA values in Handshake always have implicit handshake semantics?
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1
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165
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May 3, 2023
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Can LLVM CIRCT output negedge async reset?
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1
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256
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April 11, 2023
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CIRCT ECO in the presence of transformations
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8
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383
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March 22, 2023
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[RFC] Split Pipeline Dialect and Add Representation for Sequential Loop Scheduling
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4
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452
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March 20, 2023
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Problems with Verilator linting warning in Chisel generated code
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0
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214
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March 14, 2023
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