|
About the CIRCT category
|
|
0
|
1379
|
August 21, 2020
|
|
Help debugging CIRCT - LLDB doesn't find half the names
|
|
2
|
54
|
September 20, 2023
|
|
Handshake FuncOp creation
|
|
1
|
58
|
September 15, 2023
|
|
Error: unknown type `clock` in dialect `seq`
|
|
2
|
61
|
September 14, 2023
|
|
Firtool creates empty .sv files when it is passed "-o=."
|
|
3
|
53
|
September 10, 2023
|
|
Firtool - how do I remove the header?
|
|
1
|
46
|
September 8, 2023
|
|
Lowering to FIRRTL dialect: lowering to FModuleOp from an Op that does not have clock and reset ports
|
|
2
|
52
|
September 7, 2023
|
|
Lowering to FIRRTL dialect
|
|
2
|
59
|
September 5, 2023
|
|
[Firtool] chisel for loop to verilog
|
|
3
|
73
|
September 1, 2023
|
|
Problematic behavior of pass --convert-affine-to-loopschedule
|
|
11
|
137
|
August 31, 2023
|
|
Potential bug in CombToArith Pass?
|
|
2
|
43
|
August 31, 2023
|
|
-convert-fsm-to-sv Pass Fail
|
|
4
|
122
|
July 31, 2023
|
|
Firtool - removing unused definitions from every .sv file
|
|
3
|
229
|
July 24, 2023
|
|
Target Triples for Hardware Compilers
|
|
7
|
734
|
July 21, 2023
|
|
FIFO channel in CIRCT
|
|
13
|
329
|
July 20, 2023
|
|
Sv.reg names
|
|
4
|
117
|
July 13, 2023
|
|
[CIRCTHLS]-Hlstool Lowering Problems
|
|
0
|
102
|
July 10, 2023
|
|
Is CIRCT able to analyze Verilog
|
|
26
|
1429
|
July 9, 2023
|
|
[Question] Handshake dialect doc
|
|
2
|
104
|
July 4, 2023
|
|
Sv.wire and hw.wire
|
|
2
|
119
|
June 22, 2023
|
|
C++ or RUST to VHDL
|
|
3
|
349
|
June 10, 2023
|
|
CIRCT install not working
|
|
2
|
116
|
June 10, 2023
|
|
Some question about fsm dialect?
|
|
3
|
142
|
June 8, 2023
|
|
How to show the generic form for ops in CIRCT dialects
|
|
1
|
140
|
May 12, 2023
|
|
How to compile chisel to HW?
|
|
2
|
208
|
May 9, 2023
|
|
Should SSA values in Handshake always have implicit handshake semantics?
|
|
1
|
166
|
May 3, 2023
|
|
Can LLVM CIRCT output negedge async reset?
|
|
1
|
261
|
April 11, 2023
|
|
CIRCT ECO in the presence of transformations
|
|
8
|
387
|
March 22, 2023
|
|
[RFC] Split Pipeline Dialect and Add Representation for Sequential Loop Scheduling
|
|
4
|
462
|
March 20, 2023
|
|
Problems with Verilator linting warning in Chisel generated code
|
|
0
|
219
|
March 14, 2023
|