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About the CIRCT category
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0
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1739
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August 21, 2020
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Integration with ABC optimizer
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9
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1130
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June 23, 2025
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Lowering From LTL to Core
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3
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75
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May 12, 2025
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Firtool v1.114.1 segmentation fault with Chisel 7.0.0-RC1
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8
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102
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May 9, 2025
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Dealing with files emitted by addResource / HGLDD in firtool
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3
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44
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April 29, 2025
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CIRCT: Lowering Upstream MLIR into Verilog
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10
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358
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March 19, 2025
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Proper way to obtain arcilator-runtime.h for C++ integration
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2
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83
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February 10, 2025
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LLVM Dev Meeting CIRCT Meetup?
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15
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299
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October 25, 2024
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Operation cloning in graph regions with use before def values
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2
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44
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October 21, 2024
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[Job Ad] PhD position in Munich, Germany, on CIRCT, Yosys and Verilator
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0
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185
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October 4, 2024
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How do you code a generate (parallel for loop) in FIRRTL?
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8
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104
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September 29, 2024
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FIRRTL equivalent to Yosys's `$initstate`
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1
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60
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September 25, 2024
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Is CIRCT able to analyze Verilog
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108
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4014
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September 23, 2024
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Citing CIRCT
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1
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77
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August 8, 2024
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Lowering from CHIRRTL dialect
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2
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69
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July 16, 2024
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Compiling CIRCT with standard LLVM and MLIR packages
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3
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224
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June 15, 2024
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Conversion of `sv.assign` to `sv.alwayscomb`
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4
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150
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May 24, 2024
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Passing Chisel information to Firrtl and emit debug info for the Tywaves waveform viewer
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12
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214
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May 2, 2024
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FIRRTL specfication questions
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7
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201
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May 1, 2024
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RFC: Support zero-width integers in the comb dialect (CIRCT)
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15
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455
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April 28, 2024
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'firtool' crashes with an error when receives a 'fir' file with no main module
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4
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107
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April 16, 2024
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PSA: branches will be deleted when PRs are merged
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0
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113
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April 11, 2024
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FIRRTL CatPrimOp semantics
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9
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179
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March 29, 2024
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HGLDD wrong var_name reference?
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3
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106
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March 28, 2024
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FIRRTL Dialect InstanceOp Verilog Parameters
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6
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113
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March 18, 2024
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HGLDD format description
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5
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253
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March 15, 2024
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Firtool integration
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12
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233
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February 8, 2024
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FIRParser 'Probe'
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6
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105
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January 15, 2024
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ReleaseWithDebInfo-Clang omits LLVM & CIRCT include directories
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1
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146
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January 12, 2024
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How to export submodule ports in HW Module using `arcilator --state-file`
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8
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174
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January 3, 2024
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