Incubator

Enzyme The Enzyme project is a tool that takes arbitrary existing code as LLVM IR and computes the derivative (and gradient) of that function. torch-mlir This category is intended for questions, discussions, proposal, etc. about the mlir-npcomp incubator project, a MLIR based compiler toolkit for numerical python programs, hosted at: https://github.com/llvm/mlir-npcomp/ CIRCT The Circuit IR Compilers and Tools (CIRCT) project aims to apply MLIR and the LLVM development methodology to the domain of hardware design tools. The EDA industry has well-known and widely used proprietary and open source tools. However, these tools are often inconsistent, have usability concerns, and were not designed together into a common platform. We believe that open source design tools leveraging multiple abstractions designed around a coherent framework like MLIR can radically disrupt this industry, in the same way that open source compilers now dominate the software tool industry.

Topic	Replies	Views	Activity
About the Incubator category Incubator	0	262	August 21, 2020
First results from using LLVM CIRCT on our design CIRCT	6	198	May 19, 2022
[Community Meeting / Developer Hour] Refactoring recurring meetings torch-mlir	0	79	May 17, 2022
Writing Custom FIRRTL Passes CIRCT	2	70	May 4, 2022
[Torch-MLIR Community Meeting] 2022-05-02 torch-mlir	3	151	May 3, 2022
[RFC] Representing pipelined loops CIRCT	30	685	May 2, 2022
Handshake: Circuit with optional result CIRCT	3	92	April 22, 2022
Announcing the Torch-MLIR Developer Hour torch-mlir	1	129	April 11, 2022
Errors while running firtool, but Verilog still generated CIRCT	4	77	April 4, 2022
Always_comb warning in Verilator CIRCT	0	39	April 2, 2022
Verilog 93 output CIRCT	2	81	April 2, 2022
Is there a way to generate Verilog stripped of non-synthesis code? CIRCT	7	115	April 1, 2022
Is there a way to create a hash of synthesizable Verilog? CIRCT	1	66	March 31, 2022
Choosing the dialect for generating MLIR torch-mlir	4	113	March 30, 2022
How are the Integration tests executed flow CIRCT	2	52	March 25, 2022
Should "automatic logic" appear when firtool --verilog is specified? CIRCT	7	84	March 24, 2022
One more error from Yosys CIRCT	0	54	March 24, 2022
Longer .sv files from LLVM CIRCT than .v files from Chisel CIRCT	7	102	March 22, 2022
How can I get firtool output into a folder? CIRCT	1	55	March 22, 2022
[Torch-MLIR Community Meeting] 2022-04-04 torch-mlir	2	384	March 16, 2022
Forward pass execution with custom forward derivative Enzyme	2	70	March 10, 2022
CIRCT/MLIR dialect(s) for on-the-fly compiler generation for programmable heterogeneous (AI) accelerators? CIRCT	4	213	March 9, 2022
Old ODM videos seem unavailable CIRCT	1	88	February 28, 2022
LATTE '22 Announcement CIRCT	2	231	February 25, 2022
FIRRTL to HW assertion error CIRCT	2	101	February 23, 2022
Terminology: Instance CIRCT	2	170	February 10, 2022
HIR vs Calyx CIRCT	4	298	February 4, 2022
Reverse-Mode AD of Object-Oriented CFD Code w Enzyme Enzyme	4	243	January 22, 2022
Joining the CIRCT Discord channel? CIRCT	2	189	January 13, 2022
Is there something like sv.logic instead of sv.reg/sv.wire? CIRCT	4	211	January 5, 2022