-riscv-v-vector-bits-min is no longer needed. It defaults to the same value as whatever zvlb extension is passed -march. Using zvlb is the correct way to set the minimum VLEN. Setting it will not make the vectorizer used fixed width vectors.
-riscv-v-register-bit-width-lmul=N influences what LMUL is used. It doesn’t depend on VLEN. It defaults to 2. Setting it higher will use larger LMUL in the loop body, but may run out of registers leading to expensive spills to memory. Ideally the vectorizer would calculate register pressure for each loop and decide this for itself. I’m not sure how far along we are on making that happen.
Passing -march=rv64gcv should be enough to enable autovectorization which does not rely on VLEN. By default each vector loop iteration will operate on whole vectors and there will a scalar remainder loop to process any remaining elements that couldn’t fill a whole register.
You can pass -mllvm -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -mllvm -force-tail-folding-style=data-with-evl to get rid of the scalar remainder loop. The vectorizer will instead use a vsetvli in the loop body to limit the number of elements on the last 1 or 2 iterations of the vector loop if it can’t fill a whole vector. This is the style of vector loop shown in the RISC-V vector specification. We hope to make this the default eventually.