LLVM Weekly - #534, March 25th 2024
If you prefer, you can read the canonical version of this issue at http://llvmweekly.org/issue/534.
Welcome to the five hundred and thirty-fourth issue of LLVM Weekly, a weekly newsletter (published every Monday) covering developments in LLVM, Clang, and related projects. LLVM Weekly is brought to you by Alex Bradbury. Subscribe to future issues at http://llvmweekly.org and pass it on to anyone else you think may be interested. Please send any tips or feedback to asb@asbradbury.org, @llvmweekly or @asbradbury on Twitter, or @llvmweekly@fosstodon.org or @asb@fosstodon.org.
News and articles from around the web and events
LLVM 18.1.2 was released.
The /r/cpp subreddit C++ committee trip report for the March meeting in Tokyo is now up.
According to the LLVM calendar in the coming week there will be the following (note: US is still ahead of most countries in entering daylight savings time so meeting times may be different to usual):
- Office hours with the following hosts: Kristof Beyls, Johannes Doerfert, Amara Emerson.
- Online sync-ups on the following topics: SPIR-V, new contributors, OpenMP, Flang, MLIR, RISC-V, embedded toolchains.
- For more details see the LLVM calendar, getting involved documentation on online sync ups and office hours.
On the forums
-
Stephen Tozer shared a public service announcement on how instruction constructors are changing to iterator-only insertion.
-
Christudasan Devadasan is seeking feedback on the addition of synthetic register classes and allocation masks, intended to solve some reocurring problems with allocating vector registers in the AMDGPU backend.
-
M Zeeshan Siddiqui posted an MLIR RFC on an optimisation in the SuperVectorizer regarding the handling of misaligned data.
-
Tom Eccles started an RFC discussion on adding an interface for top level container operations in Flang FIR.
-
“byrnesj1” posted an RFC on tracking values through integral address space casts for improved alignment reasoning.
LLVM commits
-
A detailed InstCombine contributor guide is now available. 6898147.
-
Temporary DbgRecord functions were added to the DIBuilder C API to help downstream projects during the transition period. f0dbcfe.
-
3-way comparison intrinsics were introduced. 276847a.
-
As a stepping stone towards the migration to
ptradd
, the representation ofgetelementptr inrange
was changed. 0f46e31. -
A
PreferSmallerInstructions
option was added to control the AsmMatcherEmitter and used for Arm as part of a refactoring. 6854f6f, 295cdd5. -
A scheduling model was added for the SiFive-P670. c48d818.
-
Minbitwidth analysis in the superword level parallelism vectoriser was improved. 31eaf86.
-
DPValue was renamed to DbgVariableRecord, DPLabel renamed to DbgLabelRecord, and DPMarker to DbgMarker. ffd08c7, bdc77d1, 75dfa58.
-
The Hexagon backend gained support for emitting Hexagon elf attributes. 31f4b32.
-
REG_SEQUENCE
andEXTRACT_SUBREG
are now used to move between individual GPRs and GPRPair, leading to much better codegen for Zdinx (double-precision floating point in GPRs) on RV32. 576d81b. -
llvm-objdump gained
--skip-symbol[s]
options. 4946cc3.
Clang commits
-
The default linker for wasm32-wasip2 is now wasm-component-ld. d66121d.
-
clang-cl
now supports runtime feature detection of intrinsics. afec08e. -
A soft-float ABI was added for AArch64. ef395a4.
-
Lambda expressions are now accepted in C++03 mode as an extension. 2699072.
-
RISC-V profile names can now be giving for
-march
. b44771f. -
bugprone-suspicious-stringview-data-usage was added to clang-tidy. 28c1279.