Hi,
I am looking into implementation of a custom RISC-V ISA extension and was wondering if or how would a memory-to-memory instruction be supported by the clang compiler.
Situation is as follows: you have an instruction which source operand(s) are in memory (like a vector load instruction) and the destination(s) is also in memory (like a vector store instruction), i.e. there is no intermediate storage in the registers of the CPU. Also this instruction is not a control flow instruction. The data/structural hazards are taken care of by the hardware (pipeline is stalled while the instruction is executing) and the instruction would inferred manually by the programmer/part of a library.
What I am worried about is if this would work with the clang compiler, i.e. how to specify data dependencies. Suppose the C source code looks like this:
//SECTION: 0
//some modification of array arr_a, arr_b
//SECTION: 1
custom_instr(&arr_a[0], &arr_b[0], &arr_c[0], length) //source are arr_a, arr_b, output is stored in arr_c
//SECTION: 2
//arr_c gets modified further
and the instruction in assembly would be custom_instr r1,r2,r3,r4, where registers r1-r4 would store the start addresses of arr_a, arr_b, arr_c and the the length of the arrays respectively. This also means that the cycle length of this instruction is variable.
So, is there a way to implement this in clang? If so, what would be roughly the steps to implement this. Or is the idea of memory-to-memory instruction such not something the modern compilers were meant to work with?
Thanks!