Operand does not exist in operand list


Absolute LLVM newbie here. I am trying to define an add instruction which takes 2 register inputs ra and rb and writes the sum into ra.

def ADDR : F_R<0b000000,(outs) , (ins CPURegs:$rb, CPURegs:$ra),“ADDR $ra, $rb”,[(set CPURegs:$ra, (add CPURegs:$ra, CPURegs:$rb))] >;

I get this error:

error: In ADDR: Operand $rb does not exist in operand list!

Does anybody know what that means?


You need a register in the outs list too. To inform everything that your instruction produces an output. And it needs to be a different name than $ra and $rb. So let’s say $rd for destination. You need to do this:

let Constraints = “$ra = $rd”
def ADDR : F_R<0b000000,(outs CPURegs:$rd) , (ins CPURegs:$rb, CPURegs:$ra),“ADDR $ra, $rb”,[(set CPURegs:$rd, (add CPURegs:$ra, CPURegs:$rb))] >;

The Constraints line will tell the register allocation system that $ra and $rd should always be the same physical register.