Passing a 256 bit integer vector with XMM registers

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I am implementing a new calling convention for X86 which requires to pass a 256 bit integer vector with two XMM registers rather than one YMM register. For example

define <8 x i32> @add(<8 x i32> %a, <8 x i32> %b) {

%add = add <8 x i32> %a, %b

ret <8 x i32> %add

}

With march=X86-64 and mcpu=corei7-avx, llc with the default calling convention generates the following code

vextractf128 $1, %ymm1, %xmm2

vextractf128 $1, %ymm0, %xmm3

vpaddd %xmm2, %xmm3, %xmm2

vpaddd %xmm1, %xmm0, %xmm0

vinsertf128 $1, %xmm2, %ymm0, %ymm0

ret

With this new calling convention, llc would generate slightly different code inside the callee

vpaddd %xmm2, %xmm0, %xmm0

vpaddd %xmm3, %xmm1, %xmm1

ret

I am wonder how we can specify this rule. I tried to specify this in X86CallingConv.td which seems insufficient, since the number of registers is coded in TargetLoweringBase::computeRegisterProperties(). Any suggestions are appreciated!

Thanks!

Wei