[pipeline] How to distinguish the Instruction pipelines for the same instruction with different const shift value

Beginners
1

hi,
In the comment of D135441, we talked that Modern cores usually have free shifts <= 4 places for ADD instruction .etc.
But how to define the Instruction pipelines for them? It seems we can’t distinguish the const shift value in the ProcessorModel.

2

oh, maybe can refer to commit d6ac96f95