Question about porting LLVM - code selection without assembler feature

Hello all,

I am adding a new target into LLVM. However there is a assembler for that target and I just want LLVM to generate assembly. I read the document “Writing an LLVM Backend”. I am wondering to know whether I can ignore the Inst field in the following example:

class InstSP<dag outs, dag ins, string asmstr, list pattern> : Instruction {

  field bits<32> Inst;
  let Namespace = "SP";
  bits<2> op;
  let Inst{31-30} = op;       
  dag OutOperandList = outs;
  dag InOperandList = ins;
  let AsmString   = asmstr;
  let Pattern = pattern;
}
And define the instruction class of ported target as:

Lu Mitnick <king19880326@gmail.com> writes:

Hello all,

I am adding a new target into LLVM. However there is a assembler for
that target and I just want LLVM to generate assembly. I read the
document "Writing an LLVM Backend". I am wondering to know whether I
can ignore the Inst field in the following example:

I'm not an expert here so I'll defer to others.

Second, I have read the documentation of "TableGen Fundamentals" and
"The LLVM Target Independent Code Generator". But I don't know how to
fill the dag filed of instruction. like [(store IntRegs:$src,
ADDRrr:$addr)] of the following example:

def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),

               "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>;

Would anyone mind to tell me where to find the documentation of the
dag in Independent Code Generator??

Think of the DAG pattern as a LISP expression. Each level of parens is
a subtree in the DAG, so

Hi Yi-Hong,

Yes, you may go ahead and omit the Inst field. That’s used to represent the instruction encoding.

-bw

Hello David,

Thanks for your example. Is that means that DAG pattern is consist of LLVM IR instruction?? I met an example [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] of MipsInstrInfo.td, but I can’t find correspond LLVM IR instruction of “set” in “LLVM Language Reference Manual”. Is that correspond to $dst = op $b, $c?? Would you mind to tell me whether there is a reference of all possible element of DAG??

thanks a lot

yi-hong

2011/1/25 David A. Greene <greened@obbligato.org>

Lu Mitnick <king19880326@gmail.com> writes:

Hello David,

Thanks for your example. Is that means that DAG pattern is consist of
LLVM IR instruction?? I met an example [(set CPURegs:$dst, (OpNode
CPURegs:$b, CPURegs:$c))] of MipsInstrInfo.td, but I can't find
correspond LLVM IR instruction of "set" in "LLVM Language Reference
Manual". Is that correspond to $dst = op $b, $c?? Would you mind to
tell me whether there is a reference of all possible element of DAG??

Ah. No, it's not LLVM IR. It's SelectionDAG IR. The operations are
defined in include/llvm/CodeGen/ISDOpcodes.h. Each target also has its
own set of operations. For example, the x86 target has operators for
x86-ish things like odd shuffles and so forth. Since you're writing
your own target, you may end up defining some. If your target is simple
enough, you won't.

The actual nodes used in patterns are defined in
include/llvm/Target/TargetSelectionDAG.td. You'll see an almost 1:1
correspondence between ISDOpcodes.h and TargetSelectionDAG.td.

In addition, there are some special operators that TableGen recognizes.
"set" is one of them. It's pure syntactic sugar. TableGen just throws
it away. It's only there to make patterns look prettier.

To find these special operators, you can look in TargetSelectionDAG.td
for the stuff that doesn't have anything matching in ISDOpcodes.h. To
know what they do, you have to read the TableGen source, currently. :frowning:

TableGen is confusing stuff, but really powerful once you grok it.

                      -Dave