I just pushed an update (to GitHub - MPACT-ORG/llvm-project at work) with some new syntax that adds an alternate way to associate instructions with instruction behaviors, similar to what InstRW does. This update also:
- cleans up the generated CPU information to streamline the integration with instruction scheduling.
- implements forwarding in the latency management code
- does a much better job of handling various scenarios that arise with Itineraries, particularly when combined in a single target with SchedModels.
- updates the language documentation
- and a bunch of minor bug fixes
One enhancement is that you can now associate a subunit template with a set of instructions, specified the same way an InstRW works:
subunit my_add : “ADD*” (…) {…}
subunit my_sub : “SUB*” : “SUBX*” (…) {…}
You can also base a subunit on another subunit, inheriting all of its instruction bindings:
subunit my_add_sub : my_add : my_sub (…) {…}
There’s also a command line flag for tdscan (the tablegen scraper) that will generate these for a target (–gen_base_subunits). But its strictly optional.
Dimitri, I think this addresses your concerns about having to modify instruction definitions for different targets. This methodology allows you to build up arbitrary hierarchies of instruction groups, which is useful in a single target or across targets.