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About the Common Infrastructure category
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0
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192
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January 8, 2022
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[RFC] CFIFixup handling of prologues which span more than one basic block
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2
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45
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September 28, 2023
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[RFC] report_fatal_error and the default value of GenCrashDialog
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12
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220
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September 28, 2023
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[RFC] MDL: A Micro-Architecture Description Language for LLVM
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50
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16766
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September 20, 2023
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Issue with adding 72 bit registers
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13
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165
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September 14, 2023
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Implementing modulo variable expansion for MachinePipeliner
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7
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348
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September 7, 2023
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LTO, ThinLTO, and Split DWARF
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4
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410
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August 30, 2023
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Gdb < 10.1 can't read clang's DWARF v5
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15
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4333
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August 22, 2023
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[MachineLICM] Should we set RegLimit using RegisterClassInfo::getRegPressureSetLimit()?
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0
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71
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August 4, 2023
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Is it possible to use the result of an IR analysis pass in a MIR pass?
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2
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88
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August 2, 2023
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MachineScheduler: Latency of edges to call schedule boundary
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0
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94
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July 25, 2023
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[RFC] MatchTable-based GlobalISel Combiners
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12
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763
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July 19, 2023
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How to make my target output XCOFF?
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1
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93
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July 19, 2023
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RFC: New loop distribution pass for software pipelining
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2
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539
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July 3, 2023
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Porting an oddball assembler
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0
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195
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June 30, 2023
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Discussing feasibility: Generating Tablegen files for easier LLVM backend development?
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11
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287
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June 26, 2023
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Lookig for reviewers for MachineLICM + WinEH
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1
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87
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June 21, 2023
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Is there a way to have a MachineFunctionPass as a analysis dependency for ModulePass using legacy PM?
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0
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92
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June 20, 2023
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Removing debug locations from ConstantSDNodes
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0
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76
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June 15, 2023
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Is there a way to use only machine-representable types in phi-nodes before building SelectionDAG?
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1
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112
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June 13, 2023
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Basic Register Allocation Algorithm Documentation
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2
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150
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June 6, 2023
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Can I dump SelectionDAG as texts?
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3
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148
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June 1, 2023
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Exceptions and stack unwinding
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1
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144
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May 31, 2023
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RFH: -global-isel-abort=1|2
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5
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174
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May 16, 2023
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[RFC] Prefix test invocations with the given tool for llvm-lit
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0
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113
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May 13, 2023
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When There Are No Bytes
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14
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794
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May 9, 2023
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How to handle pointer relocation in LLVM?
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0
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142
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May 6, 2023
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Is there any way to define custom calling convention without modifying llvm source code?
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2
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228
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May 4, 2023
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[RFC] Let MVT generated and restore MVT into llvm/CodeGen
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3
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489
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May 4, 2023
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[RFC] Let Intrinsics.td emit IIT_Info TypeSig
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5
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350
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April 26, 2023
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