[RFC][TargetTransformInfo] Add an option to supply cache line size if not provided by the target?

Hello all,

I’d like to kindly ask for feedbacks on the following patch: ⚙ D127342 [TargetTransformInfo] Added an option for the cache line size.

Here is the background:

For certain passes like loop data prefetch, loop cache analysis, we need to call TargetTransformInfo::getCacheLineSize() to obtain the cache line size of the target. However, there are a number of targets that do not have getCacheLineSize() implemented so the cache line size obtained would just be zero, which essentially disables the use of those passes.

What we proposed in D127342 is that we add an opt/llc option “-cache-line-size” (default value of 64) under TargetTransformInfo, and use it as the cache line size if not provided by the target, or to override the target cache line size when specified by the user. Hence if TTIImpl.getCacheLineSize() returns 0 for certain targets, we can still obtain a valid cache line size number to proceed with loop data prefetch or loop cache analysis.

I am wondering if what D127342 proposed makes sense? One concern is that it might break if we encounter computers with no cache (in which case the cache line size returned should indeed be zero), but we are thinking that “not having cache is an exception (at best) rather than the norm, so it doesn’t make much sense that the default assumes no cache”.

Looking forward to comments from everybody :slightly_smiling_face:

Microcontrollers that have no cache are pretty common. I think I’d prefer to leave it to the maintainers of specific targets to decide whether a default cache size makes sense.

(Adding an option to override the target seems fine.)

Thanks for the reply! It does make lots of sense.

According to your comment, regarding the option I guess I could just make the option override the target iff the option is specified by the user, like the following?

unsigned TargetTransformInfo::getCacheLineSize() const {
  return CacheLineSize.getNumOccurrences() > 0 
             ? CacheLineSize
             : TTIImpl->getCacheLineSize();
}

https://reviews.llvm.org/D58736
by David Greene
A more elaborate approach.

Thanks for the reference, I will take a deeper look.