Hi,
I’m try to lower the store LLVM-IR instruction as per the following LLVM IR program:
*** IR Dump After Module Verifier ***
define void @storeloadi32() {
%ptr = alloca i32
store volatile i32 12, i32* %ptr
ret void
}
The target instruction is associated to the store like this:
def MOVSUTO_A_iSLr : CLPFPU_A_iSLr<0b1000001101,
(ins IMM32Operand:$ImmA, FPUaRegisterOperand:$RegB),
(outs ),
,
“movsuto_a\t$ImmA,$RegB”,
[(store i32:$ImmA, i16:$RegB)],NoItinerary> {
The selection DAG seems to be correct, but a FrameIndex of 0 as been introduced :
Optimized legalized selection DAG: BB#0 ‘storeloadi32:’
SelectionDAG has 6 nodes:
t0: ch = EntryToken
t5: ch = store<Volatile ST4[%ptr]> t0, Constant:i32<12>, FrameIndex:i16<0>, undef:i16
t6: ch = CLPISD::RET_FLAG t5
ISEL: Starting pattern match on root node: t5: ch = store<Volatile ST4[%ptr]> t0, Constant:i32<12>, FrameIndex:i16<0>, undef:i16
The lowering correctly catches the store and morphs to right MOVSUTO_A_iSLr MC instruction:
Initial Opcode index to 331
Skipped scope entry (due to false predicate) at index 339, continuing at 354
Morphed node: t5: ch = MOVSUTO_A_iSLr<Mem:Volatile ST4[%ptr]> Constant:i32<12>, FrameIndex:i16<0>, t0
ISEL: Match complete!
Then instruction selection try to lower the FrameIndex node !!! This failed…
ISEL: Starting pattern match on root node: t2: i16 = FrameIndex<0>
Initial Opcode index to 0
Match failed at index 0
LLVM ERROR: Cannot select: t2: i16 = FrameIndex<0>
How to discard this FrameIndex<0> ?