Hi,
The problem is with a pattern that has a vt in it: the “vtInt …” printed below the error message. Could you run llvm-tblgen from a debugger and show the stack trace from where the error occurred?
Change
// list Pattern = [(store v1i16:$rs1, (add (v1i32 (bitconvert i32:$rbase)), (shl (v1i32 (sext v1i16:$roffset)), (v1i32 (build_vector uimm2:$rshift)))))];
To
// list Pattern = [(store (v1i16 $rs1), (add (v1i32 (bitconvert (i32 $rbase))), (shl (v1i32 (sext (v1i16 $roffset))), (v1i32 (build_vector uimm2:$rshift)))))];
i.e. replace “type:$x” with “(type $x)”.
Hi Celine,
What LLVM version is this, and does it reproduce with the trunk?
I ran into a weird issue with this signature a few months back, and it turned out to be a bug in how tblgen eliminated types when inferring patterns:
https://reviews.llvm.org/D61705
If this is reproducible on trunk with some easy to apply patch, I could take a look?
Pete
Change
// list Pattern = [(store v1i16:$rs1, (add (v1i32 (bitconvert i32:$rbase)), (shl (v1i32 (sext v1i16:$roffset)), (v1i32 (build_vector uimm2:$rshift)))))];
To
// list Pattern = [(store (v1i16 $rs1), (add (v1i32 (bitconvert (i32 $rbase))), (shl (v1i32 (sext (v1i16 $roffset))), (v1i32 (build_vector uimm2:$rshift)))))];
i.e. replace “type:$x” with “(type $x)”.
Hi Celine,
What LLVM version is this, and does it reproduce with the trunk?
I ran into a weird issue with this signature a few months back, and it turned out to be a bug in how tblgen eliminated types when inferring patterns:
https://reviews.llvm.org/D61705
If this is reproducible on trunk with some easy to apply patch, I could take a look?
Pete
Could you run llvm-tblgen with -print-records and show the parts that define “bos” and the pattern inside of it?
Could you run llvm-tblgen with -print-records and show the parts that define “bos” and the pattern inside of it?
Thanks.
Looking at the InOperandList, the rs1, rbase, etc. have register class prefixes, e.g. MGPR:$rs1. In the pattern they don’t have them. The error you saw (“rs1 must be an identifier”) was caused by tablegen being unable to match the rs1 in the pattern with any of the instruction operands.
Could you change the pattern to
[(OpNode (v1i16 MGPR:$rs1), (add (v1i32 (bitconvert (i32 SGPR32:$rbase))), (shl (v1i32 (sext (v1i16 MGPR:$roffset))), (v1i32 (build_vector (i32 uimm2:$rshift))) )))]
Thanks.
Looking at the InOperandList, the rs1, rbase, etc. have register class prefixes, e.g. MGPR:$rs1. In the pattern they don’t have them. The error you saw (“rs1 must be an identifier”) was caused by tablegen being unable to match the rs1 in the pattern with any of the instruction operands.
Could you change the pattern to
[(OpNode (v1i16 MGPR:$rs1), (add (v1i32 (bitconvert (i32 SGPR32:$rbase))), (shl (v1i32 (sext (v1i16 MGPR:$roffset))), (v1i32 (build_vector (i32 uimm2:$rshift))) )))]
The problem is with a different pattern. One that takes a valuetype as a parameter (for example something like sext_inreg).
The problem is with a different pattern. One that takes a valuetype as a parameter (for example something like sext_inreg).