TableGen pattern


I am trying to convert the subtree (vector_shuffle v2f32, v2f32
(build_vector imm1, imm2)) to a machine instruction that takes 2
v2f32's and 2 immediates. I tried the following table gen pattern :

(set v2f32Reg:$dst, (vector_shuffle v2f32Reg:$src1, v2f32Reg:$src2,
imm:$c1, imm:$c2)))

Table gen barfs about type inference contradiction for build_vector.
What am I doing wrong and how can I achieve converting to the
aforesaid machine instruction?


What version of llvm are you using? ISD::VECTOR_SHUFFLE node has changed so the shuffle mask is no longer explicit operands. Rather it's now part of the ShuffleVectorSDNode class.