x86 instructions EFLAGS in TableGen


Here is one question regarding the LLVM TableGen:

Which file in the llvm/lib/Target/X86 folder describes how the bits in the EFLAGS register are modified by the x86 instructions? For example, in the "X86InstrInfo.td" file, lines 2134-2135, it says:

let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in {
def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", >;

So it says the Defs of CLC is EFLAGS, but actually the CLC instruction only clears the "CF" flag in the EFLAGS register and has nothing to do with the other bits of EFLAGS. So which files in this folder describes the fact that CLC only modifies the CF bit?

Thank you in advance,
Antonin Reitz

We don’t model the eflags at that level. With maybe the exception of the direction flag. It’s just not that useful to the compiler to have the exact bits that are changed. And I’m not even sure we would ever emit CLC on our own.

Agreed, I looked at whether it was worth modeling each sub-flag a while ago and it didn’t seem worth it back then:


Of course it’s a microbenchmark of what I was looking at back then… Might still be worth doing. At the time I remember that GCC did really well on each sub-flag, but I think they did their magic through simple peepholes instead of fully modeling stuff. Maybe we can do more of that first?

Also, IIRC Chandler had looked into EFLAGS some more recently.

We are using SETcc+TEST when we need to keep a flag live across a call these days. It’s done by pass just looking at the condition code of the flag consumer and copying that condition code to a SETcc before the call and the TEST checks if the register written by the SETcc is zero or not after the call.