[AArch64][ABI] should we add more fixed vector type wider than 128-bit?

[Allen]

Hi, all

• Now, we have some new arm64 targets supported SVE, whose vector register width may be larger than 128. For example, if the vscale=4 for a special target, the type <vscale x 4 x i32> is actually the same as <16 x i32>, ie. its corresponding fixed vector width is 512-bit.

• We have already defined calling convention for scalable vector types and fixed vector types, whose vector register width is less or equal to 128-bit, but we have not defined the calling convention for these fixed vector types, whose vector register width is larger than 128. See
  https://github.com/llvm/llvm-project/blob/0e27cbe1879f400d64088d8770803e884782a34e/llvm/lib/Target/AArch64/AArch64CallingConvention.td#L110C2-L110C2

• So my question is, should we supplement the calling conventions for these data types, whose vector register width is larger than 128 ? For example, I come across a related compile issue record on [AArch64] compile crash on "Call operand has unhandled type" · Issue #69694 · llvm/llvm-project · GitHub.

Thanks!

[paulwalker-arm]

FYI: [AArch64] Prevent argument promotion of vector with size > 128 bits by kawashima-fj · Pull Request #70034 · llvm/llvm-project · GitHub should fix the compiler crash you’ve referenced. I know there’s still work needed to fix the root cause within the code generator but for now this fix should alleviate the problem without needing to create a new ABI.

[Allen]

Thanks very much, I’ll check that PR70034.

[Allen]

Now, above PR merged already, and they are different issue, so may be still need some discussion about the calling convention of fixed vector type, which is wider than 128-bit.
For example, the most important thing is to determine whether to transfer parameters through stacks or registers. Which is appropriate?

[Allen]

Fixed with PR70847 now, thanks @paulwalker-arm