CodeGen instructions and patterns

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#1

Is there a generic function that gives the machine instructions and their patterns given in the .td files of a backend specification ?
or a subset which match a certain opcode ?
otherwise how are the machine instructions being accessed/matched for instruction selection ?

-Omer

#2

Hi Omer,

Is there a generic function that gives the machine instructions and their patterns given in the .td files of a backend specification ?
or a subset which match a certain opcode ?

I'm not aware of any dump utility functions to display that information concisely. I agree such a thing would be useful.

otherwise how are the machine instructions being accessed/matched for instruction selection ?

Have a look at the code in SelectionDAGISel.

Regards,
-Jim

#3

otherwise how are the machine instructions being accessed/matched for instruction selection ?

Have a look at the code in SelectionDAGISel.

I am looking at the ARM backend.
In specific, the instruction selection.
In Select(N), I only see ad-hoc matches on the basis of the opcode in the provided SDNode of the DAG, and then getMachineNode() is being used to generate the machine instruction.
Am I understanding this correctly ?

Consider the following multiply add insstruction, given in ARMInstrInfo.td

def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC32, “mla”, “\t$Rd, $Rn, $Rm, $Ra”,
[(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>

How do I get this instruction and it corresponding pattern in the selector ?

-Omer

#4

(readding cc llvmdev)

otherwise how are the machine instructions being accessed/matched for instruction selection ?

Have a look at the code in SelectionDAGISel.

I am looking at the ARM backend.
In specific, the instruction selection.
In Select(N), I only see ad-hoc matches on the basis of the opcode in the provided SDNode of the DAG, and then getMachineNode() is being used to generate the machine instruction.
Am I understanding this correctly ?

That’s just the target-specific part. Also look in lib/CodeGen/SelectionDAG.

You may find the debug output from the compiler useful. Try running llc with the “-debug-only=isel” command line option. That will give lots of information about how the selector is going about figuring out which patterns to use.

-Jim