Custom RISC-V processor can be selected via `-mcpu` in `llc` but not in `clang`

Clang Frontend Using Clang
1

Hi,

I have added a scheduling model for a RISC-V vector processor to LLVM. I have included the SchedMachineModel definition in llvm/lib/Target/RISCV/RISCV.td and added it to section RISC-V processors supported as follows:

def : ProcessorModel<"vicuna", VicunaModel, [FeatureStdExtM,
                                             FeatureStdExtC,
                                             FeatureStdExtV]>;

I have then successfully built LLVM and Clang for RISC-V by using the cmake options -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_PROJECTS=clang -DLLVM_TARGETS_TO_BUILD=RISCV. The custom processor can be used with llc as follows:

$ llc -mtriple riscv32 -mattr=+experimental-v -mcpu=vicuna ...

Clang also lists the custom processor as a supported CPU with following command:

$ clang -menable-experimental-extensions --target=riscv32 -print-supported-cpus --print-supported-cpus -mcpu=?
clang version 14.0.0 (https://github.com/llvm/llvm-project.git 499f1ca79f232faae09b1793a994d1a22ba403cd)
Target: riscv32
Thread model: posix
InstalledDir: /home/michael/Documents/prog/riscv-llvm/build/bin
Available CPUs for this target:

	generic-rv32
	generic-rv64
	rocket-rv32
	rocket-rv64
	sifive-7-rv32
	sifive-7-rv64
	sifive-e20
	sifive-e21
	sifive-e24
	sifive-e31
	sifive-e34
	sifive-e76
	sifive-s21
	sifive-s51
	sifive-s54
	sifive-s76
	sifive-u54
	sifive-u74
	vicuna

Use -mcpu or -mtune to specify the target's processor.
For example, clang --target=aarch64-unknown-linux-gui -mcpu=cortex-a35

However, when I attempt to actually select the custom processor via -mcpu or -mtune, I get the following error for -mcpu:

$ clang -menable-experimental-extensions --target=riscv32 -march=rv32imcv0p10 -mcpu=vicuna ...
clang: error: the clang compiler does not support '-mcpu=vicuna'

and the following error for -mtune:

$ clang -menable-experimental-extensions --target=riscv32 -march=rv32imcv0p10 -mtune=vicuna ...
error: unknown target CPU 'vicuna'
note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, generic, rocket, sifive-7-series

Why is that? What am I missing?

Thanks for any pointers!

2

Have you also added your processor to llvm/include/llvm/Support/RISCVTargetParser.def? I think that might be the interface Clang speaks to rather than the .td file.

3

Thanks, that was the missing piece.