I’m defining the instructions for a microcontroller.
Most of the instructions have two explicit input registers, but the output register is implicit for a given instruction.
For example, the output register for FADD instruction is FA_ROUTADD while the output register for the FMUL instruction is FA_ROUTMUL.
But the FA_ROUTADD nor the FA_ROUTMUL appears in the assembler syntax for the instruction.
def FADD_A_rr : CLPFPU_A_rr_Inst<0b0000000101,
[(set f32:$FA_ROUTADD, (fadd f32:$RegA, f32:$RegB))] >;
def FMUL_A_rr : CLPFPU_A_rr_Inst<0b0000001101,
[(set f32:$FA_ROUTMUL, (fmul f32:$RegA, f32:$RegB))] >;
The TableGen generated code consider these two instructions as three operands instructions.
In the MCInst data structure, RegA and RegB are respectively the second and third operands.
The place for the first operand seems to be reserved for the implicit output register.
If I understand the need for such implicit register information, it is not clear for me, when and who will populate this first operand.
My problem is that the default generated disassembler for now populate the RegA and RegB in the first and second operands.
While the InstPrinter try to print the second and the third operands.
What is the most elegant way to address this issue? Any suggestions are welcome.
Regards, Dominique Torette.