I have been reading assembly code for RISC-V, ARM64, and My ISA and came across what I think is an arithmetic anomaly across all three (and likely more) LLVM implementations.
It is commonly known as “the double Rounding Problem”::
Ref: 13-bitn.pdf
The source code in question is of the form:
float f, h;
f = h * 1.425;
and in all cases the compiler produces something like: ISA independent assembly:
CVTFD Rt,Rh
FMUL Rt,Rt,Rconstant
CVTDF Rf,Rt
This sequence of code is subject to the double rounding problem described in the referenced documents unless the FMUL is performed in Round-to-Nearest-Odd rounding mode described therein. Yet, no implementations (that I know of) implements RNO and even if they did it would add several more instructions to the sequence to set the RM and then reset the RM. Yech.
I talked to my compiler writer and apparently LLVM chooses this method whenever the FP constant is not exact in (float or 32-bit) form and that the compiler suite is just trying to do its best.
I do not expect anyone to do anything about this, I just though your numerical analysist would get a laugh at the delicacy of trying to get IEEE 754 exactly right in light of producing optimized code.
Mitch