floating point exceptions in compare instructions

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1

Looking at the llvm code I have the impression that ordered fp
comparisons should use exception throwing instructions. Is it true?

Thanks,
Rafael

2

Nope, you want non-trapping instructions. If you use trapping instructions, C99 functions like isgreater will not work correctly with NAN's.

-Chris

3

Nope, you want non-trapping instructions. If you use trapping
instructions, C99 functions like isgreater will not work correctly with
NAN's.

How do I know when to use a trapping instruction? For example consider
this C function:

4

I'm not sure, it's possible GCC is wrong: my understanding is that that should return false on nan, not trap. However, the ARM ISA manual is also confusing to me:

FCMPES Operation:

if ConditionPassed(cond) then
   if (Sd is a NaN) or (Sm is a NaN) then
     raise Invalid Operation exception
   FPSCR N flag = if (Sd < Sm) then 1 else 0
   FPSCR Z flag = if (Sd == Sm) then 1 else 0
   FPSCR C flag = if (Sd < Sm) then 0 else 1
   FPSCR V flag = if (Sd and Sm compare as unordered) then 1 else 0

How could this instruction ever set FPSCR V=1?

-Chris