How can I model an instruction that gets broken down into two µ-ops?

[tschuett]

[RFC] MDL: A Micro-Architecture Description Language for LLVM

TL;DR: We’ve created a DSL and compiler for modeling micro-architecture that handles a very broad class of architectures - CPU, GPUs, VLIWs, DSPs, ML accelerators, and embedded devices. This effort grew out of a need to quickly develop and experiment with high-quality compilers and tools to facilitate rapid architecture exploration. We named the DSL “MDL” for “Microarchitecture Description Language”. While being significantly more expressive than TableGen’s Schedules and Itineraries used in LL…

?