How To Call / Debug properly llc for RISC-V

Code Generation RISCV
1

Hi, I am completely new to LLVM Backend, and I am trying to do some experiments with the RISC-V target. I’d like to codegen a simple ll and print IR after every pass.

I manually built LLVM and enabled all backends.

I started with the following simple command:

clang -O3 --target=riscv64 -march=rv64i -S bitswap.c -o bitswap.s

It works well and generate the expected assembly RISC-V code.

After this, I tried using llc to be able to print the IR after every pass:

clang bitswap.c -O3 -S -emit-llvm -o bitswap.ll
llc bitswap.ll -march=riscv64 --print-after-all -o -

But it asserts with the following error:

LLVM ERROR: RV64 target requires an RV64 CPU

What am I doing wrong here ? How is that I can compile to RISC-V with clang, but not with llc ?

2

You still need to pass —target=riscv64 to clang. IR isn’t portable between targets.

1 Like
3

Thanks, it’s working correctly with these flags