New AVX512{VL,BW,DQ} features enabled in LLVM

Hi all!

We (Intel compiler team, Moscow) would like to announce enabling in
LLVM/Clang the additional AVX512 instructions, introduced in the
newest release of Intel Architecture Instruction Set Extensions
Programming Reference
(https://software.intel.com/sites/default/files/managed/c6/a9/319433-020.pdf).

This ISA adds 3 new features:

- AVX512VL ("vector length" extension): many of AVX512 instructions
were extended to support %XMM and %YMM registers, not only %ZMM.

- AVX512BW ("byte and word" instructions): new instructions for vector
elements lengths of 8 and 16 bits .

- AVX512DQ ("doubleword and quadword" instructions): new instructions
for vector elements lengths of 32 and 64 bits (those not implemented
in AVX512F).

We've implemented or working on:

- 3 features above (1000+ instructions);

- lowering for many of masked operations , so it can be utilized in vectorizers;

- intrinsics, compatible with those from gcc/icc;

- thousands of encoding and lowering tests for these features;

Contribution details:

- We are going to contribute new features into LLVM/Clang starting today.

- The major contributor and the maintainer of these features in our
team is Robert Khasanov. You may address him your questions on
AVX512{BW,DQ,VL} implementation and support in LLVM.

- Our LLVM patches were kindly reviewed and approved by Elena
Demikhovsky (Intel), the author of AVX512 support in LLVM.

Your feedback is welcome!

More information:

- James Reinders blog post:
https://software.intel.com/en-us/blogs/additional-avx-512-instructions

- SDE emulator supporting new features (use SKX target):
https://software.intel.com/en-us/articles/intel-software-development-emulator

- ISA: https://software.intel.com/sites/default/files/managed/c6/a9/319433-020.pdf

Intel Compiler Team, Moscow.