I read that you do implement these operations in your backend some time ago. (http://llvm.1065342.n5.nabble.com/llvm-dev-Questions-about-load-store-incrementing-address-modes-td87577.html).
The DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) function never works for me.
Can you show me a code fragment in C which is translated into pre/post dec/inc load/store? Then I will be able to experiment with msp430 (there seems to have the processing of such cases).
Or may be I can look at your backend?
I may be wrong, but I think this is meant to support instruction such as
mov r0,(r1)+, which is the corresponding of
*ptr++ = val; - the exact syntax of the assembler is of course varying depending on which processor it is for. I’m using PDP-11 syntax, as that is the first processor I saw this in. I don’t know if mps430 supports this type of instruction at all. The combine part of this is obviously to perform analysis and spot that there are “small” loads/stores that can be merged together into larger ones, e.g.
*s++ = 'h'; *s++ = 'e'; *s++ = 'l'; *s++ = 'l'; *s++ = 'o'; can be combined to something like
*((uint32_t*)s)++ = 'hell'; *s++='o'; - this is not a proper syntax for C or C++, but I’ve written it that way to show what it does - the transformation is done on the generated code, so how it’s written in C is not really relevant.
(There are probably a whole heap or rules about how and when this can be used, such as alignment needs to be right, etc)