We would like to request for including Xtensa backend to LLVM upstream. The first batch of patches is about to be accepted.
This thread is a continuation of the discussion [RFC] Tensilica Xtensa (ESP32) backend . According to @clattner recommendation we open separate topic for discussion about inclusion our work into the project.
Since last update we continued to work on the project and update patches in Phabricator. Currently Xtensa backend is ported on LLVM release 15.0.0.
The process of reviewing patches in Phabricator also significantly accelerated. An additional five patches have been approved, for a total of 8 out of 10 patches now approved. We are updating the last two patches according to the comments and will publish them soon. Many thanks to @Sterling-Augustine and all participants!
This has been discussed a number of times, and I believe all previous discussions were generally positive towards inclusion of this target into LLVM. The linked thread already discussed how the target meets the policy to accept a new experimental target, and that all seems fine.
So, I think at this point, you only need to wait for the entire 10-patch series to be approved. After the last 2 patches have been reviewed and approved, I think you should be good to go!
I would like to share new information, that is important for the review process of the Xtensa backend patches in Phabricator. There is now a publicly available summary of Xtensa ISA by Cadence: https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/ip/tensilica-ip/isa-summary.pdf . I hope this documentation makes the review process easier, and perhaps more members of the LLVM community can help with the review of patches.
Nice! That’s great to hear, and I’m sure it’ll be helpful for quite a few people to have this full ISA document publicly available. (Also, the name of the document makes me laugh – “Instruction Set Architecture Summary” – at 700 pages, that’s the longest summary I’ve ever seen!)
The process seems to get stuck again. So this message is intended kick it off and claim that we are alive and continue Xtensa support in LLVM, but some thing are beyond our capabilities
I wonder what is the status of the Xtensa backend in regard to completeness? As we work on capstone-autosync project, allowing generating the Capstone disassembly code from the TableGen files, would that cover all supported instructions (including optional extensions)?
