Shortage of Mips reviewers

It seems that many individuals with expertise in Mips have shifted their focus elsewhere. In addition, with the departure of @atanasyan as the Mips code owner, we are facing a shortage of resources for reviewing Mips-related code.

Recently, there has been a surge in Mips-related patches. I find myself frequently assigned as a reviewer for these patches. While I am generally confident in handling matters unrelated to ISA, I must admit that I feel uneasy when it comes to dealing with aspects like ISA, ABIs, GNU behavior, and similar technical nuances. I want to be transparent that my concern lies not specifically with Mips itself, but rather with the specific components that are impacted (Clang driver, MC, compiler-rt, etc.).

Having someone who knows the ISA and can dedicate time to reviewing would be immensely beneficial. Having someone who can test (given that Mips has so many ABIs) would also be really helpful. I am curious if anyone would be willing to volunteer their expertise or if anyone knows of potential individuals who could provide assistance. It’s possible that volunteers might only have a very limited amount of time to spare, so having a pool of volunteers would be helpful.

Folks who have been added as reviewers as I observed: @BradSmith @jrtc27
Folks who have a lot of Mips devices and “try to provide a little help nevertheless”: @xen0n
MIPS Backend Code Owner - #5 by davidchisnall @davidchisnall

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Please do tag me on them for things ISA related. I haven’t got any MIPS hardware anymore and don’t actively work on it (FreeBSD just dropped MIPS support), but I was sufficiently traumatised by MIPS that I can probably remember enough ISA details to help out.


…unless they’re about MIPSr6, which is an almost completely different ISA that I have never touched.

Please do tag me for MIPS issues.

I’m not familiar with LLVM codebase but I do know many MIPS details including Release 6.


We could definitely use help getting the ARCH=mips port of the Linux kernel in better shape when building with LLVM.

The lack of a code owner on the LLVM side (for MIPS) has been worrying. I understand needing to take a break, but I will encourage every code owner to have some succession process in mind. I think we could a much better job of that in LLVM in general.

For what it’s worth, Rust has downgraded Mips to a tier 3 target (i.e., we no longer ship pre-compiled artifacts), in large part due to the lack of a Mips code owner or group reviewer in LLVM.