What is the correct method to model caches (data cache, instruction cache) while developing an LLVM backend. Is it done in one of the TableGen (.td) files? How do Intel, RISC-V etc. do it?
What is the correct method to model caches (data cache, instruction cache) while developing an LLVM backend. Is it done in one of the TableGen (.td) files? How do Intel, RISC-V etc. do it?