What is the correct method to model caches (data cache, instruction cache) while developing an LLVM backend. Is it done in one of the TableGen (.td) files? How do Intel, RISC-V etc. do it?
As of writing this comment, there does not seem to be a standard method, but, the RFC [System Model] Introduce a target system model did propose a way. It seems to be still under review!
This post is related to my other question TableGen: Apart from registers, do we also model internal memory?