the following test code get from llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
define void @lmul1_and_2() nounwind {
%v2 = alloca <vscale x 2 x i64>
ret void
}
and both riscv64 and aarch64 generate assemble with sub/add sp (see detail Compiler Explorer) , such as aarch64:
str x29, [sp, #-16]! // 8-byte Folded Spill
addvl sp, sp, #-1 // sub sp
addvl sp, sp, #1 // add sp
ldr x29, [sp], #16
combine addvl sp, sp, #-1 and addvl sp, sp, #1, the sp in fact doesn’t change, so them are redundant ?