Topics tagged riscv

Topic	Replies	Views	Activity
Merging RISCVToolChain and BareMetal toolchains Clang Frontend riscv , clang	8	839	May 4, 2026
[RFC] RVCC: An LLVM Incubator for High-Performance RISC-V Compiler Optimizations Incubator riscv	18	978	April 24, 2026
Promoting load/something/store to atomics on single-hart virtual target RISCV riscv	2	78	April 17, 2026
[RFC] Add RISE RISC-V Runners GitHub riscv , libc	7	154	April 9, 2026
[RFC] RISC-V ropi-rwpi profile with gp-based runtime data addressing RISCV riscv , llvm	5	209	April 2, 2026
Beating -Oz for a specific codebase Beginners riscv , llvm	5	341	March 25, 2026
Beijing LLVM Meetup, March 20, 2026 LLVM Project riscv , jit	0	124	March 13, 2026
TVM + LLVM flow for custom NPU: Where should the Conv2d tiling and memory management logic reside? IR & Optimizations riscv , llvm	0	68	February 24, 2026
[Funded PhD] Intelligent Compilation Infrastructure for Scientific Simulation (LLVM/MLIR/HPC) @ UTS, Sydney Job Postings gpu , riscv , clang , llvm , mlir	0	185	February 11, 2026
How to add a register only custom datatype Clang Frontend riscv , clang , llvm	0	35	February 3, 2026
Israel LLVM Meetup Group - February 18th 2026 Community riscv , clang , llvm , mlir	0	110	February 3, 2026
Beijing LLVM Meetup LLVM Project riscv , llvm	0	141	January 29, 2026
Help with building compiler-rt for RISCV target Runtimes riscv , llvm	9	182	January 18, 2026
Beijing LLVM Tech Meetup LLVM Project riscv , llvm	0	90	January 6, 2026
Search path of libclang_rt.profile.a Using Clang riscv , clang	0	67	December 31, 2025
Optimizing Load-multiple and Store-multiple on LLVM RISCV riscv , llvm	1	201	December 22, 2025
Senior LLVM Compiler Developer(s) @ Ubitium, Germany Job Postings riscv , llvm	0	254	December 3, 2025
LLVM backed for handling UMUL8 and UMUL16 for PSIMD RISC-v RISCV riscv , llvm	0	52	December 2, 2025
RISC-V Roundtable Meeting Notes US Developer Meeting riscv	4	280	November 3, 2025
[RFC]Modify RegMask Settings of Scalar Library Functions to Reduce Spills RISCV riscv , llvm	1	115	October 14, 2025
TableGen custom Instruction "Operand not declared in matcher" Code Generation riscv , llvm	7	219	September 19, 2025
[RFC] New analysis for Polynomial Hash recognition Loop Optimizations riscv , llvm	4	496	September 8, 2025
Dynamically adding/loading RISC-V (custom) instruction information during runtime LLVM Project riscv , clang , llvm	3	184	August 27, 2025
Software shadow call stack run-time support for RISC-V Sanitizers riscv	4	234	August 7, 2025
Llvm-objdump: disassembling unknown instructions LLVM Project riscv , llvm	1	113	July 14, 2025
How to disable section merging? LLD gpu , riscv , clang , llvm	14	436	July 9, 2025
Move / Remove `vcix` dialect MLIR riscv	48	1321	July 3, 2025
How can I save the callgraph in a separate section .callgraph in an ELF file? LLD core , gpu , riscv , clang , llvm	0	74	July 2, 2025
MLIR Compiler School & Workshop in Cambridge/UK, September 8-12 Announcements riscv , llvm , mlir	0	553	June 12, 2025
Linking errors when using Sleef_expfx_u10rvvm2 RISCV riscv , clang	3	113	June 9, 2025