Suppose I have an instruction which defines a subregister of a register R and at the same time it uses the whole register R. Is it possible to tie the def and the use?

More precisely, the instruction reads two registers (Xi and Yi) and writes one of them (Xi). The “i” (the register number) must be the same for Xi and Yi. Xi and Yi belong to different register classes.

There are register tuples which can help with tying the source operands, and Operand::Constraints for tying dst and src, but it seems that the Operand::Constrains expects the tied registers to be the same, so I can’t tie Xi and Xi+Yi.

Is it possible to model such constraint? If not, is there any workaround?