[RFC] Parallelizing (Target-Independent) Instruction Selection

Hi,
Though there exists lots of researches on parallelizing or scheduling optimization passes, If you open up the time matrices of codegen(llc -time-passes), you’ll find that the most time consuming task is actually instruction selection(40~50% of time) instead of optimization passes(10~0%). That’s why we’re trying to parallelize the (target-independent) instruction selection process in aid of JIT compilation speed.

The instruction selector of LLVM is an interpreter that interpret the MatcherTable which consists of bytecodes generated by TableGen. I’m surprised to find that the structure of MatcherTable and the interpreter seems to be suitable for parallelization. So we propose a prototype that parallelizes the interpreting of OPC_Scope children that are possibly time-consuming. Here is some quick overview:

We add two new opcodes: OPC_Fork and OPC_Merge. During DAG optimization process(utils/TableGen/DAGISelMatcherOpt.cpp). OPC_Fork would be added to the front of scope(OPC_Scope) children which fulfill following conditions:

  1. Amount of opcodes within the child exceed certain threshold(5 in current prototype).
  2. The child is reside in a sequence of continuous scope children which length also exceed certain threshold(7 in current prototype).
    For each valid sequence of scope children, an extra scope child, where OPC_Merge is the only opcode, would be appended to it(the sequence).

In the interpreter, when an OPC_Fork is encountered inside a scope child, the main thread would dispatch the scope child as a task to a central thread pool, then jump to the next child. At the end of a valid “parallel sequence(of scope children)” an OPC_Merge must exist and the main thread would stop there and wait other threads to finish.

About the synchronization, read-write lock is mainly used: In each checking-style opcode(e.g. OPC_CheckSame, OPC_CheckType, except OPC_CheckComplexPat) handlers, a read lock is used, otherwise, a write lock is used.

Finally, although the generated code is correct, total consuming time barely break even with the original one. Possible reasons may be:

  1. The original interpreter is pretty fast actually. The thread pool dispatching time for each selection task may be too long in comparison with the original approach.
  2. X86 is the only architecture which contains OPC_CheckComplexPat that would modify DAG. This constraint force us to add write lock on it which would block other threads at the same time. Unfortunately, OPC_CheckComplexPat is probably the most time-consuming opcodes in X86 and perhaps in other architectures, too.
  3. Too many threads. We’re now working on another approach that use larger region, consist of multiple scope children, for each parallel task for the sake of reducing thread amount.
  4. Popular instructions, like add or sub, contain lots of scope children so one or several parallel regions exist. However, most of the common instruction variants(e.g. add %reg1, %reg2) is on “top” among scope children which would be encountered pretty early. So sometimes threads are fired, but the correct instruction is actually immediately selected after that. Thus lots of time is wasted on joining threads.

Here is our working repository and diff with 3.9 release: https://bitbucket.org/mshockwave/hydra-llvm/branches/compare/master%0D3.9-origin#diff
I don’t think the current state is ready for code reviewing since there is no significant speedup. But it’s very welcome for folks to discuss about this idea and also, whether current instruction selection approach had reached its upper bound of speed.(I ignore fast-isel by mean since it sacrifices too much on quality of generated code. One of our goals is to boost the compilation speed while keeping the code quality as much as possible)

Feel free to comment directly on the repo diff above.

About the “region approach” mentioned in the third item of possible reasons above. It’s actually the “dev-region-parallel” branch, but it still has some bugs on correctness of generated code. I would put more detail about it if the feedback is sound.

NOTE: There seems to be some serious bugs in concurrent and synchronization library of old gcc/standard libraries. So it’s strongly recommended to use the latest version of clang to build our work.

B.R

It seems like you're trying to do extremely fine-grained parallelization, which usually doesn't end well. It seems to me that it would make much more sense to go for parallelization at the module level (i.e. multiple functions in parallel) or possibly basic block level or possibly at the selection DAG level itself, i.e. at the level of selection DAG nodes.

As far as the instruction selection itself is concerned, I've been wondering in the past whether somebody has looked into profile-guided optimization of the matcher (i.e. profile-guided optimization of the matcher table by TableGen).

Cheers,
Nicolai

How much of this 40-50% is spent in the matcher table? I though most of the overhead was inherent to SelectionDAG?
Also why having such a fine grain approach instead of trying to perform instruction selection in parallel across basic blocks or functions?

I suspect you won’t gain much for too much added complexity with this approach.

I forgot to add: did you try to enable fast-isel instead? In the context of a JIT this is a quite common approach.

Nicolai Hähnle <nhaehnle@gmail.com> 於 2016年11月30日 上午4:56 寫道:

It seems like you’re trying to do extremely fine-grained parallelization, which usually doesn’t end well. It seems to me that it would make much more sense to go for parallelization at the module level (i.e. multiple functions in parallel) or possibly basic block level or possibly at the selection DAG level itself, i.e. at the level of selection DAG nodes.

I think JIT compilation tend to compile small amount of DAG nodes(so, small Function and BasicBlock) each time in no matter method-based or traced-based strategies, so I guess it wouldn’t get significant benefit from it. (Correct me if I’m not right)

As far as the instruction selection itself is concerned, I’ve been wondering in the past whether somebody has looked into profile-guided optimization of the matcher (i.e. profile-guided optimization of the matcher table by TableGen).

That’s an interesting thing idea. I ‘m also wondering whether we can “cache” the selection result or selection “path” of matchers like inline cache in dynamic compilation.
Maybe you can talk more about your thoughts?

B.R
McClane

Mehdi Amini <mehdi.amini@apple.com> 於 2016年11月30日 上午5:16 寫道:

Hi,
Though there exists lots of researches on parallelizing or scheduling optimization passes, If you open up the time matrices of codegen(llc -time-passes), you’ll find that the most time consuming task is actually instruction selection(40~50% of time) instead of optimization passes(10~0%). That’s why we’re trying to parallelize the (target-independent) instruction selection process in aid of JIT compilation speed.

How much of this 40-50% is spent in the matcher table? I though most of the overhead was inherent to SelectionDAG?
Also why having such a fine grain approach instead of trying to perform instruction selection in parallel across basic blocks or functions?

I suspect you won’t gain much for too much added complexity with this approach.

I forgot to add: did you try to enable fast-isel instead? In the context of a JIT this is a quite common approach.

Well, as I mentioned at the bottom of my first letter, one of our goal is to boost the compilation speed while keeping the quality of generated code as much as possible. And fast-isel doesn’t perform really well on quality of generated code.
Perhaps users of fast-isel would use multi-tier compilation model and take fast-isel as baseline compiler I guess.

B.R.
McClane

Mehdi Amini <mehdi.amini@apple.com> 於 2016年11月30日 上午5:14 寫道:

Hi,
Though there exists lots of researches on parallelizing or scheduling optimization passes, If you open up the time matrices of codegen(llc -time-passes), you’ll find that the most time consuming task is actually instruction selection(40~50% of time) instead of optimization passes(10~0%). That’s why we’re trying to parallelize the (target-independent) instruction selection process in aid of JIT compilation speed.

How much of this 40-50% is spent in the matcher table? I though most of the overhead was inherent to SelectionDAG?

Do you mean DAG operations like adding SDNode to CSENodes? Could you talk a little bit more?

Also why having such a fine grain approach instead of trying to perform instruction selection in parallel across basic blocks or functions?

JIT compilation tends to compile small amount of DAG nodes each time, and also, most of the JIT strategies tend to merge several instructions(e.g. all of the hot instructions) into single basic block or function, so I guess it wouldn’t get significant speedup on overall performance if we handle only one(or few) compilation unit each time.(correct me if I’m wrong)

B.R.
McClane

Mehdi Amini <mehdi.amini@apple.com> 於 2016年11月30日 上午5:14 寫道:

Hi,
Though there exists lots of researches on parallelizing or scheduling optimization passes, If you open up the time matrices of codegen(llc -time-passes), you’ll find that the most time consuming task is actually instruction selection(40~50% of time) instead of optimization passes(10~0%). That’s why we’re trying to parallelize the (target-independent) instruction selection process in aid of JIT compilation speed.

How much of this 40-50% is spent in the matcher table? I though most of the overhead was inherent to SelectionDAG?

Do you mean DAG operations like adding SDNode to CSENodes? Could you talk a little bit more?

Yes: building the DAG and mutating the DAG (performing the combine/legalize stage, with continuous CSE).
What does your profile show? Do you have some example IR out of your frontend that I could process with opt/llc and profile?

Also why having such a fine grain approach instead of trying to perform instruction selection in parallel across basic blocks or functions?

JIT compilation tends to compile small amount of DAG nodes each time, and also, most of the JIT strategies tend to merge several instructions(e.g. all of the hot instructions) into single basic block or function, so I guess it wouldn’t get significant speedup on overall performance if we handle only one(or few) compilation unit each time.(correct me if I’m wrong)

If you have one function and a very small IR as you seem to indicate here, I wouldn’t expect parallelizing the matcher table to be worthwhile (I’d like to see a profile…).
I rather think that if the matcher table is high on the profile, a “PGO" approach as suggested by Nicolai is likely to help the most.

Also, you should really measure the difference on the generated code between fast-isel and SelectionDAG, as in practice it may not be that high for the kind of IR you have. Sometimes, we’ve seen fast-isel even gets better generated code by matching pattern across basic blocks.

Bekket McClane <bekket.mcclane@gmail.com> 於 2016年11月30日 上午10:55 寫道:

Mehdi Amini <mehdi.amini@apple.com> 於 2016年11月30日 上午9:50 寫道:

Mehdi Amini <mehdi.amini@apple.com> 於 2016年11月30日 上午5:14 寫道:

Hi,
Though there exists lots of researches on parallelizing or scheduling optimization passes, If you open up the time matrices of codegen(llc -time-passes), you’ll find that the most time consuming task is actually instruction selection(40~50% of time) instead of optimization passes(10~0%). That’s why we’re trying to parallelize the (target-independent) instruction selection process in aid of JIT compilation speed.

How much of this 40-50% is spent in the matcher table? I though most of the overhead was inherent to SelectionDAG?

Do you mean DAG operations like adding SDNode to CSENodes? Could you talk a little bit more?

Yes: building the DAG and mutating the DAG (performing the combine/legalize stage, with continuous CSE).
What does your profile show? Do you have some example IR out of your frontend that I could process with opt/llc and profile?

The “large” one, to simulate the scenario that someone just want to speed up the building speed of a large project instead of JIT usages:

The mailing system seems to block the message due to the large IR file
Here is the google drive link:
https://drive.google.com/open?id=0BwIwAHzsWbekX04wRkFuUGs4dUU

zlib-longest-match.ll (12.9 KB)

If I run: " clang -march=x86-64 zlib-longest-match.ll -mllvm -time-passes -c -O2” on this I get this top 5:

Total Execution Time: 0.1896 seconds (0.2101 wall clock)

—User Time— --System Time-- --User+System-- —Wall Time— — Name —
0.0024 ( 18.4%) 0.0450 ( 25.4%) 0.0473 ( 25.0%) 0.0536 ( 25.5%) X86 DAG->DAG Instruction Selection
0.0005 ( 4.1%) 0.0192 ( 10.8%) 0.0197 ( 10.4%) 0.0226 ( 10.8%) Combine redundant instructions
0.0010 ( 7.7%) 0.0128 ( 7.2%) 0.0138 ( 7.3%) 0.0144 ( 6.9%) Induction Variable Simplification
0.0011 ( 8.7%) 0.0101 ( 5.7%) 0.0112 ( 5.9%) 0.0116 ( 5.5%) Loop Strength Reduction
0.0002 ( 1.3%) 0.0083 ( 4.7%) 0.0085 ( 4.5%) 0.0101 ( 4.8%) Early CSE

And the DAG detail is:

0.0004 ( 22.6%) 0.0137 ( 39.4%) 0.0141 ( 38.6%) 0.0168 ( 40.3%) DAG Combining 1
0.0003 ( 18.8%) 0.0106 ( 30.6%) 0.0109 ( 30.0%) 0.0118 ( 28.1%) Instruction Selection
0.0002 ( 14.6%) 0.0022 ( 6.4%) 0.0025 ( 6.8%) 0.0034 ( 8.1%) Instruction Scheduling
0.0001 ( 8.2%) 0.0027 ( 7.9%) 0.0029 ( 7.9%) 0.0033 ( 7.9%) DAG Legalization
0.0001 ( 8.0%) 0.0026 ( 7.6%) 0.0028 ( 7.6%) 0.0032 ( 7.7%) Type Legalization

The -time-passes option is nice, but I like to look at the profiler better in general, so I ran a profiler (Instruments) on the backend only (without running the optimizer!) using: llc -march=x86-64 zlib-longest-match.ll -O2 -time-passes -disable-verify -time-compilations 100
(It will repeat the codegen 100 times which helps getting enough runtime to have a meaningful profile)

I get (focusing on the “Instruction Selection” part:

Running Time Self (ms) Symbol Name
20.5ms 3.2% 0.2 llvm::SelectionDAGISel::DoInstructionSelection()
18.9ms 3.0% 0.5 (anonymous namespace)::X86DAGToDAGISel::Select(llvm::SDNode*)
17.7ms 2.8% 6.9 llvm::SelectionDAGISel::SelectCodeCommon(llvm::SDNode*, unsigned char const*, unsigned int)
3.9ms 0.6% 0.4 (anonymous namespace)::X86DAGToDAGISel::CheckComplexPattern(llvm::SDNode*, llvm::SDNode*, llvm::SDValue, unsigned int, llvm::SmallVectorImpl<std::__1::pair<llvm::SDValue, llvm::SDNode*> >&)

Note that the percentage if with respect to the total time, so it seems to me that you’re trying to parallelize a function that takes ~3% of the backend, which doesn’t play well with Amdahl.

Best,

Mehdi Amini <mehdi.amini@apple.com> 於 2016年11月30日 上午11:23 寫道:

Mehdi Amini <mehdi.amini@apple.com> 於 2016年11月30日 上午9:50 寫道:

Mehdi Amini <mehdi.amini@apple.com> 於 2016年11月30日 上午5:14 寫道:

Hi,
Though there exists lots of researches on parallelizing or scheduling optimization passes, If you open up the time matrices of codegen(llc -time-passes), you’ll find that the most time consuming task is actually instruction selection(40~50% of time) instead of optimization passes(10~0%). That’s why we’re trying to parallelize the (target-independent) instruction selection process in aid of JIT compilation speed.

How much of this 40-50% is spent in the matcher table? I though most of the overhead was inherent to SelectionDAG?

Do you mean DAG operations like adding SDNode to CSENodes? Could you talk a little bit more?

Yes: building the DAG and mutating the DAG (performing the combine/legalize stage, with continuous CSE).
What does your profile show? Do you have some example IR out of your frontend that I could process with opt/llc and profile?

The “large” one, to simulate the scenario that someone just want to speed up the building speed of a large project instead of JIT usages:

<Task.ll>

The normal one, from one of the test cases in LLVM, to simulate JIT compilation usage:

<zlib-longest-match.ll>

If I run: " clang -march=x86-64 zlib-longest-match.ll -mllvm -time-passes -c -O2” on this I get this top 5:

Total Execution Time: 0.1896 seconds (0.2101 wall clock)

—User Time— --System Time-- --User+System-- —Wall Time— — Name —
0.0024 ( 18.4%) 0.0450 ( 25.4%) 0.0473 ( 25.0%) 0.0536 ( 25.5%) X86 DAG->DAG Instruction Selection
0.0005 ( 4.1%) 0.0192 ( 10.8%) 0.0197 ( 10.4%) 0.0226 ( 10.8%) Combine redundant instructions
0.0010 ( 7.7%) 0.0128 ( 7.2%) 0.0138 ( 7.3%) 0.0144 ( 6.9%) Induction Variable Simplification
0.0011 ( 8.7%) 0.0101 ( 5.7%) 0.0112 ( 5.9%) 0.0116 ( 5.5%) Loop Strength Reduction
0.0002 ( 1.3%) 0.0083 ( 4.7%) 0.0085 ( 4.5%) 0.0101 ( 4.8%) Early CSE

And the DAG detail is:

0.0004 ( 22.6%) 0.0137 ( 39.4%) 0.0141 ( 38.6%) 0.0168 ( 40.3%) DAG Combining 1
0.0003 ( 18.8%) 0.0106 ( 30.6%) 0.0109 ( 30.0%) 0.0118 ( 28.1%) Instruction Selection
0.0002 ( 14.6%) 0.0022 ( 6.4%) 0.0025 ( 6.8%) 0.0034 ( 8.1%) Instruction Scheduling
0.0001 ( 8.2%) 0.0027 ( 7.9%) 0.0029 ( 7.9%) 0.0033 ( 7.9%) DAG Legalization
0.0001 ( 8.0%) 0.0026 ( 7.6%) 0.0028 ( 7.6%) 0.0032 ( 7.7%) Type Legalization

The -time-passes option is nice, but I like to look at the profiler better in general, so I ran a profiler (Instruments) on the backend only (without running the optimizer!) using: llc -march=x86-64 zlib-longest-match.ll -O2 -time-passes -disable-verify -time-compilations 100
(It will repeat the codegen 100 times which helps getting enough runtime to have a meaningful profile)

I get (focusing on the “Instruction Selection” part:

Running Time Self (ms) Symbol Name
20.5ms 3.2% 0.2 llvm::SelectionDAGISel::DoInstructionSelection()
18.9ms 3.0% 0.5 (anonymous namespace)::X86DAGToDAGISel::Select(llvm::SDNode*)
17.7ms 2.8% 6.9 llvm::SelectionDAGISel::SelectCodeCommon(llvm::SDNode*, unsigned char const*, unsigned int)
3.9ms 0.6% 0.4 (anonymous namespace)::X86DAGToDAGISel::CheckComplexPattern(llvm::SDNode*, llvm::SDNode*, llvm::SDValue, unsigned int, llvm::SmallVectorImpl<std::__1::pair<llvm::SDValue, llvm::SDNode*> >&)

Note that the percentage if with respect to the total time, so it seems to me that you’re trying to parallelize a function that takes ~3% of the backend, which doesn’t play well with Amdahl.

Cheers! Thanks for the profiling
I even don’t know the -time-compilations options.
We’ll verify our assumption again.

B.R.
McClane

JFYI, if you haven’t tested the quality of FastIsel code on your platform, do. FastIsel frequently generates quite decent code for some of the architectures we support. I’ve heard of folks using it for high tier JITs. (I don’t personally do so, but it’s on my list of things to re-evaluate at some point.)