I strongly support the addition of a CHERI-like architecture to the target-independent parts of LLVM.
The downstream work on CHERI has already been improving LLVM’s semantics around pointers, provenance, and address spaces – which has all been useful for non-CHERI users as well. Getting a hardware capability pointer model like CHERI supported upstream will be great to really put an emphasis on the need to be serious about getting all this stuff nailed down, specified, and working properly.
The proposal to add the non-standard RISC-V vendor extensions, and maintain them for the long-term even after “Y” is standardized, worries me. But I’m happy to leave it up to the RISC-V maintainer group to decide how they feel about that.