RVV Vector Predication IR Lowering Question

Code Generation RISCV
1

Hi, I want to catch up with the codegen process in LLVM to generate the rvv code, now I know that we use SLP and Loop Vectorizor to perform the auto-vectorization in LLVM, and the TargetTransform info also provide some target-specific information for better rvv codegen quality like LMUL choice etc. But I’m still noticed that in LLVM, Vector Predication IR is a better choice for scalable vector code generation, how can i find this part for rvv lowering or instruction selection process in source code? I mean which file can i find in LLVM source code to perform such Vector Predication IR Lowering/Selection for rvv? Thanks!

2

the Vector Predication (VP) intrinsics will be lowered to ISD nodes like ISD::VP_ADD by SelectionDAGBuilder. Then each target is free to lower those nodes however they want.
RISCV, for instance, convert ISD::VP_* into their own ISD nodes, like RISCVISD::ADD_VL, and specify the ISel patterns in TableGen using their TG counterparts, like riscv_add_vl.

2 Likes
4

Thanks a lot, that’s a big help.

5

Here’s is the first patch to use VP intrinsics in the loop vectorizer ⚙ D99750 [LV, VP] RFC: VP intrinsics support for the Loop Vectorizer (Proof-of-Concept)

1 Like
6

Thanks bro, I will keep track with that patch to follow the progress.