MLIR and FPGA targets

Hi,

Is there any work being done on compiling for FPGA targets like AMD XILINX?
My understanding is that some of the steps can be done with open source MLIR and LLVM but there is remaining a close source “Vivado” compiler to do the final compiling for the XILINX target.
Is there anyone working on an open source solution for the last compile to FPGA step?
I think there would be benefits in this area, or facilitate more optimizations also simulate the FPGA, so one can simulate how it will behave before actually applying it to hardware.

If no one is working on this area, I would like to make a start on it, but only if other people also think it would be helpful to the community as a whole.

Suggest you check out CIRCT: https://circt.llvm.org/ Part of CIRCT includes a flow to generate synthesizable Verilog, similar to Vivado HLS/Vitis HLS. There’s no MLIR effort to implement further synthesis and place and route flows that I’m aware of, but there are other (non-MLIR) open source tools in this area. To me the next step in this direction would be to implement a synthesis and logic mapping flow in MLIR that would reduce to FPGA primitives. As one gets further down the stack, building these flows without intimate device knowledge becomes more complicated. Personally, I’m heavily involved with building MLIR toolchains for AIEngine devices. see: GitHub - Xilinx/mlir-aie: An MLIR-based toolchain for Xilinx Versal AIEngine-based devices. Here it’s a little bit easier to build new flows that provide a low-level device model than with FPGA logic.

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