For background on these calls, see here.
Reminder: the purpose is to coordinate between active contributors. If you have support questions etc then it’s best to post to LLVM’s Discourse or Discord.
We have a call every alternate Thursday at 4pm BST and recently have moved to the LLVM Foundation’s Zoom. If you have topics to discuss, please email me ahead of time and I can add them to the agenda.
Dial-in details:
We have a shared calendar that may help in keeping track, which is
accessible through:
Agenda:
- LLVM 15 branch (planned for July 26th)
- Any bugfixes under review or expected to be posted soon, that should be prioritised?
- psABI public review period (until 29th August)
- D129735 [WIP][RISCV] Add new pass to transform undef to zero-init for
vector values. https://reviews.llvm.org/D129735 (subregister liveness
and V extension) - D129178 [RISCV] Enable the GlobalMerge pass for RISC-V
https://reviews.llvm.org/D129178 - D129824 [RISCV] Set triple based on -march flag which can be deduced in
more generic way https://reviews.llvm.org/D129824 - D130068 [RISCV][NFCI] Set TransientStackAlignment and rely on it rather
than RVV-specific logic on RVV-less functions
https://reviews.llvm.org/D130068 - Seperate debuginfo and RISC-V
https://github.com/llvm/llvm-project/issues/56642 D130206 CodeGen: use
address form for DW_AT_high_pc on RISCV https://reviews.llvm.org/D130206
D130190 [Driver] Error for -gsplit-dwarf with RISC-V linker relaxation
https://reviews.llvm.org/D130190 - riscv_vector.h intrinsics and
__attribute__((__target__("foo"))riscv_vector.h intrinsics should be target-gated, not preprocessor-gated · Issue #56592 · llvm/llvm-project · GitHub - AOB
- Next meeting: Thu 4th August 2022, 4pm BST
Best,
Alex