RISC-V LLVM sync-up call 9th June 2022

Code Generation RISCV
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For background on these calls, see here.

Reminder: the purpose is to coordinate between active contributors. If you have support questions etc then it’s best to post to LLVM’s Discourse or Discord.

We have a call every alternate Thursday at 4pm BST and as of last time have moved to the LLVM Foundation’s Zoom. If you have topics to discuss, please email me ahead of time and I can add them to the agenda.

Note: I’m unlikely to be able to dial in today and have done a less thorough job than usual of collecting topics. I’m on holiday, but was aiming to dial in - unfortunately my hotel has horrendously poor internet access so that won’t be possible. As such, please do be sure to respond to this thread with additional agenda topics or just raise them in the meeting.

Dial-in details:

We have a shared calendar that may help in keeping track, which is
accessible through:

Agenda:

Best,

Alex

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I had posted here an analysis of the -fprofile-instr-generate bug mentioned by Craig during the call. My analysis was based on an automatically reduced IR. Looking at the original IR, my conclusions about how to fix this weren’t correct because the reduced IR lacked the section assignment, and that changes things. I’ll post a patch to fix the issue.